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ds07-05309-3e fujitsu semiconductor data sheet microprocessor sparclite cmos 32-bit embedded controller mb86830 series mb86831/832/833/834/835/836 n description the mb86830 series is a sparclite * 1 series of risc architecture processors, providing high performance for a variety of embedded applications. conforming to the sparc * 2 architecture, the mb86830 series is upward code- compatible with the conventional products in the sparclite family. when running at 100 mhz, the mb86830 series provides performance of 121 vax-mips. the mb86830 series has on-chip data and instruction caches, allowing the processor to operate independently of the wait time for external memory. the independent instruction bus and internal data bus serve as high-bandwidth interfaces between the iu (integer unit) and caches. the mb86830 series also contains an internal multiplier circuit that facilitates interfacing with external devices, thereby providing high performance with continuous cache hits. the dram controller supports both of edo and fast-page mode drams. the interrupt controller (irc) supports eight channels of interrupts, allowing a trigger mode and mask to be set for each of the channels. to get the most out of the system with a minimum number of external circuits, the mb86830 series supports chip select output, program- mable wait state generator, and page mode dram interfaces. the combination of these features of the mb86830 series achieves high levels of speed, flexibility, and efficiency, making it a line of ideal controllers for a variety of low-cost, high-performance embedded systems. *1 : sparclite is a trademark of sparc international, inc. in the united states. fujitsu microelectronics, inc. has been granted permission to use the trademark. *2 : sparc is a registered trademark of sparc international, inc. in the united states. sparc is based on technology developed by sun microsystems, inc. n pac k ag e 176-pin plastic qfp mb86831/832/834 144-pin plastic lqfp mb86833/835/836 144-pin plastic fbga mb86836 (fpt-176p-m01) (fpt-144p-m08) (bga-144p-m02)
mb86830 series 2 n features ? iu (integer unit) maximum operating frequency : 120 mhz sparc architecture v8e conforming with 32-bits general register :136 / register window : 8 ? instruction cash the entry lock function is supported ? data cache no cash controlling function supported the entry lock function is supported ? biu (bus interface unit) purifetchi baffa :1 write buffer :4 the burst mode is supported programmable chip selection function :6 programmable weight state control :6 for 8/16/32-bits bus automatic insertion function of idling cycle after rom region is accessed for burst mode rom ? with internal clock multiplication circuit ? sleep mode (low power consumption mode) supported ? with dram controller (except on the mb86836) ? with interrupt request controller (irc) ? on-chip general-purpose 16-bit timer (mb86836 only):1 channel (equivalent to the mb86942) ? support for the jtag test port (mb86836 only)
mb86830 series 3 n product lineup *1:mb86836 108 mhz version is under developement. *2: the general-purpose timer on the mb86836 is a subset of the prescaler-integrated 16-bit timer on the mb86942. for the type supporting only the internal clock mode, refer to the document for the mb86941/942. part number item mb86831 mb86832 mb86833 mb86834 MB86835 mb86836 cpu maximum frequency (mhz) 66/80 66/80/100 66 108/120 84 90/108* 1 bus maximum frequency (mhz) 40 33 40 ancillary version register (0000) 16 (0001) 16 (0002) 16 (0003) 16 (0004) 16 (0001) 16 instruction cache 4 kb/2 way 8 kb/2 way 1 kb/direct 16 kb/2 way 4 kb/2 way 8 kb/2 way data cache 2 kb/2 way 8 kb/2 way 1 kb/direct 16 kb/2 way 2 kb/2 way 8 kb/2 way cache size change function no 8/4/2/1 kb selectable no adr pin adr<27:2> adr<23:2> adr<27:2> adr<23:2> adr enhancement (asisel) no adr<31:2> adr<27:2> adr<31:2> adr<27:2> clock gear function no ye s dsu no ye s n o ye s n o dram controller 4bank 1bank 4bank 1bank no jtag test port no ye s general porpose 16-bit timer* 2 no 1ch internal pull-up/down resister pin p63 p63, p162 to p164 no p41 to p44, p79 internal power supply (v dd3 ) 3.3 v 2.5 v 3.3 v 2.5 v i/o power supply (v dd5 ) 3.3 v to 5.0 v 3.3 v package sqfp176 fpt-176p-m01 24 24 mm lqfp144 fpt-144p- m08 20 20 mm sqfp176 fpt-176p- m01 24 24 mm lqfp144 fpt-144p- m08 20 20 mm lqfp144 fpt-144p- m08 20 20 mm fbga144 bga- 144p-m02 12 12 mm
mb86830 series 4 n for package and part number note:refer topackage dimensions for details in each package. n differences 1.package ? mb86831/832/834 : qfp176 ? mb86833/835/836 : lqfp144 ? mb86836 : fbga144 2.pin array ? mb86831/832/834 : the pin is interchangeable.however, the terminal of mb86834 is the pull-up resistor none. ? mb86833/835 : the pin is interchangeable. ? mb86836 : mb86833/835, from which dramc related pins are deleted and to which one channel of general-purpose 16-bit timer and the jtag pin are added. 3.maximum operation frequency ? mb86831 : 66mhz/80mhz ? mb86832 : 66mhz/80mhz/100mhz ? mb86833 : 66mhz ? mb86834 : 108mhz/120mhz ? MB86835 : 84mhz ? mb86836 : 90mhz/108mhz 4.power-supply voltage * : the power-supply voltage is different (refer to electric characteristics) depending on the condition of the operation frequency. 5.cache memory package mb86831 mb86832 mb86833 mb86834 MB86835 mb86836 fpt-176p-m01 yes yes no yes no no fpt-144p-m08 no no yes no yes yes bga-144p-m02 no no no no no yes power-supply voltage mb86831 mb86832 mb86833 mb86834 MB86835 mb86836 internal power-supply voltage 3.3 v 2.5 v 3.3 v 2.5 v i/o power-supply voltage 3.3 v or 5.0 v 3.3 v 3.3 v 3.3 v cache memory mb86831 mb86832 mb86833 mb86834 MB86835 mb86836 instruction cash 4 kb/2 way 8 kb/2 way 1 kb/direct 16 kb/2 way 4 kb/2 way 8 kb/2 way data cash 2 kb/2 way 8 kb/2 way 1 kb/direct 16 kb/2 way 2 kb/2 way 8 kb/2 way
mb86830 series 5 6.register 7.clock gear ? mb86832/833/834/835/836 : supported ? mb86831 : no supported 8.external signal *:ras1# to ras3# and dwe1# to dwe3# deletion. register name mb86831/832/833/835/836 mb86834 instruction cache invalidate register (icinvld) map of asi = 0x0c, adr = 0x00001000(bank1) asi = 0x0c, adr = 0x80001000(bank2) map of asi = 0x0c, adr = 0x00008000(bank1) asi = 0x0c, adr = 0x80008000(bank2) data cache invalidate register (dcinvld) map of asi = 0x0e, adr = 0x00001000(bank1) asi = 0x0e, adr = 0x80001000(bank2) map of asi = 0x0e, adr = 0x00008000(bank1) asi = 0x0e, adr = 0x80008000(bank2) register name mb86831 mb86832 mb86833 mb86834 MB86835 mb86836 ancillary version register (ver2) (00) 16 (01) 16 (02) 16 (03) 16 (04) 16 (01) 16 item mb86831 mb86832 mb86833 mb86834 MB86835 mb86836 asisel pin function no multiplex of adr<31:28> and asi<3:0> multiplex of adr<27:24> and asi<3:0> multiplex of adr<31:28> and asi<3:0> multiplex of adr<27:24> and asi<3:0> dsu (debugging support unit) no yes no yes no dram controller 4bank supported 4bank supported 1bank supported* 4bank supported 1bank supported* no general-purpose 16-bit timer no wih 1ch. prescaler (equivalent to mb86942) jtag no support pull-up resistor or pull-down resistor inclusion inclusion no inclusion
mb86830 series 6 n pin assignment (top view) (fpt-176p- m01) (top view) (fpt-144p-m08) 132 133 176 89 45 44 1 88 index 108 109 144 73 37 36 1 72 index 144 1 3 7 11 15 18 22 26 30 33 35 36 a b c d e f g h j k l m n 143 2 4 6 10 14 19 23 27 31 34 38 37 141 142 5 8 12 16 20 24 28 32 41 40 39 138 139 140 9 13 17 21 25 29 45 44 42 43 134 135 136 137 49 48 46 47 130 131 132 133 53 52 50 51 126 127 128 129 57 56 55 54 123 122 124 125 61 60 59 58 119 118 120 121 65 64 63 62 115 114 116 117 101 97 93 89 85 81 68 67 66 111 112 113 104 100 96 92 88 84 80 77 70 69 109 110 106 103 99 95 91 86 82 78 76 74 71 108 107 105 102 98 94 90 87 83 79 75 73 72 12345678910111213 (bga-144p- m02) v dd3 (v dd2 ) ; internal power supply : 8 gnd : 12 v dd5 (v dd1 ) ; i/o power supply : 8
mb86830 series 7 ? mb86831/832/834 v dd3 :for internal power supply. v dd5 :for i/o power supply. reserved:this pin must be open. *:the pull-up resistor is built into. however, there is no pull-up resistor in mb86834. [ ]:pin is added with mb86832/834. please use this terminal by the opening in case of mb86831-66 and 80. pin no. pin symbol pin no. pin symbol pin no. pin symbol pin no. pin symbol pin no. pin symbol 1 v dd3 37 d<4> 73 bmreq# 109 adr<11> 145 float# 2 d<31> 38 bmode8# 74 ovf# 110 ready# 146 pdown# 3 d<30>39 v ss 75 samepage# 111 v dd3 147 wkup# 4 d<29> 40 d<3> 76 as# 112 adr<12> 148 reset# 5 d<28> 41 d<2> 77 v dd3 113 adr<13> 149 v ss 6 v ss 42 d<1> 78 rdwr# 114 adr<14> 150 idleen 7 bmode16# 43 d<0> 79 rdyout# 115 adr<15> 151 clksel1 8 d<27> 44 v dd3 80 cs5# 116 v ss 152 clksel0 9 d<26>45 v ss 81 cs4# 117 adr<16> 153 clkext 10 d<25> 46 dwe3# 82 v dd5 118 adr<17> 154 clkin 11 d<24> 47 dwe2# 83 v ss 119 adr<18> 155 v dd5 12 v dd5 48 dwe1# 84 cs3# 120 adr<19> 156 irq11 13 d<23> 49 dwe0# 85 cs2# 121 v dd5 157 irq10 14 d<22> 50 v ss 86 cs1# 122 adr<20> 158 irq9 15 d<21> 51 v dd5 87 cs0# 123 adr<21> 159 irq8 16 d<20> 52 ras0# 88 v ss 124 adr<22> 160 v ss 17 v ss 53 ras1# 89 v dd3 125 adr<23> 161 reserved 18 d<19> 54 ras2# 90 be3# 126 mexc# 162 [asisel *] 19 d<18> 55 ras3# 91 be2# 127 v ss 163 [emubrk# *] 20 d<17> 56 v dd3 92 be1# 128 adr<24> 164 [emuenb# *] 21 d<16> 57 cas0# 93 be0# 129 adr<25> 165 v dd3 22 btest# 58 cas1# 94 v ss 130 adr<26> 166 [emusd3] 23 v dd3 59 cas2# 95 noncache# 131 adr<27> 167 [emusd2] 24 d<15> 60 cas3# 96 reserved 132 v dd3 16 [emusd1] 25 d<14> 61 v ss 97 reserved 133 v ss 169 [emusd0] 26 d<13> 62 doe# 98 adr<2> 134 asi<3>[/adr<28>] 170 v dd5 27 d<12> 63 clksel2 * 99 adr<3> 135 asi<2>[/adr<29>] 171 v ss 28 v ss 64 error# 100 v dd5 136 asi<1>[/adr<30>] 172 [emud3] 29 d<11> 65 lock# 101 adr<4> 137 asi<0>[/adr<31>] 173 [emud2] 30 d<10> 66 ctest# 102 adr<5> 138 v ss 174 [emud1] 31 d<9> 67 v dd5 103 adr<6> 139 v dd5 175 [emud0] 32 d<8> 68 breq# 104 adr<7> 140 irl<3>/irq15 176 v ss 33 v dd5 69 pbreq# 105 v ss 141 irl<2>/irq14 34 d<7> 70 bgrnt# 106 adr<8> 142 irl<1>/irq13 35 d<6> 71 bmack# 107 adr<9> 143 irl<0>/irq12 36 d<5> 72 v ss 108 adr<10> 144 v dd3
mb86830 series 8 ? mb86833/835 v dd3 :for internal power supply. v dd5 :for i/o power supply. reserved:this pin must be open. pin no. pin symbol pin no. pin symbol pin no. pin symbol pin no. pin symbol 1v dd3 37 v dd3 73 v dd3 109 v dd3 2 bmode16# 38 d<2> 74 be3# 110 mexc# 3 d<28> 39 d<1> 75 be2# 111 adr<23> 4 d<27> 40 d<0> 76 be1# 112 asi<3>/adr<24> 5 d<26> 41 dwe0# 77 be0# 113 asi<2>/adr<25> 6 d<25> 42 ras0# 78 reserved 114 asi<1>/adr<26> 7 d<24> 43 cas0# 79 reserved 115 asi<0>/adr<27> 8 d<23> 44 cas1# 80 noncache# 116 irl<3>/irq15 9v ss 45 v ss 81 v ss 117 v ss 10 d<22> 46 cas2# 82 adr<2> 118 irl<2>/irq14 11 d<21> 47 cas3# 83 adr<3> 119 irl<1>/irq13 12 d<20> 48 doe# 84 adr<4> 120 irl<0>/irq12 13 d<19> 49 error# 85 adr<5> 121 float# 14 d<18> 50 lock# 86 adr<6> 122 pdown# 15 d<17> 51 ctest# 87 adr<7> 123 wkup# 16 d<16> 52 breq# 88 adr<8> 124 reset# 17 btest# 53 pbreq# 89 adr<9> 125 idleen 18 v dd5 54 v dd5 90 v dd5 126 v dd5 19 v ss 55 v ss 91 v ss 127 v ss 20 d<15> 56 bgrnt# 92 adr<10> 128 clksel2 21 d<14> 57 bmack# 93 adr<11> 129 clksel1 22 d<13> 58 bmreq# 94 adr<12> 130 clksel0 23 d<12> 59 ovf# 95 adr<13> 131 clkext 24 d<11> 60 samepage# 96 adr<14> 132 clkin 25 d<10> 61 as# 97 adr<15> 133 irq11 26 d<9> 62 rdwr# 98 adr<16> 134 irq10 27 d<8> 63 rdyout# 99 adr<17> 135 irq9 28 bmode8# 64 cs5# 100 ready# 136 irq8 29 v dd3 65 v dd3 101 v dd3 137 v dd3 30 v ss 66 v ss 102 v ss 138 v ss 31 d<7> 67 cs4# 103 adr<18> 139 reserved 32 d<6> 68 cs3# 104 adr<19> 140 asisel 33 d<5> 69 cs2# 105 adr<20> 141 d<31> 34 d<4> 70 cs1# 106 adr<21> 142 d<30> 35 d<3> 71 cs0# 107 adr<22> 143 d<29> 36 v dd5 72 v dd5 108 v dd5 144 v dd5
mb86830 series 9 ? mb86836 v dd3 : 2.5-v power pin (for supplying internal power) vpd: test pin. usually fixed to the l level. v dd5 : 3.3-v power pin (for supplying i/o power) * : with an internal pull-down resistor reserved : leave the pin open. pin no. pin symbol pin no. pin symbol pin no. pin symbol pin no. pin symbol 1v dd3 37 v dd3 73 v dd3 109 v dd3 2 bmode16# 38 d<2> 74 be3# 110 mexc# 3 d<28> 39 d<1> 75 be2# 111 adr<23> 4 d<27> 40 d<0> 76 be1# 112 asi<3>/adr<24> 5 d<26> 41 trst# 77 be0# 113 asi<2>/adr<25> 6 d<25> 42 tck* 78 vpd 114 asi<1>/adr<26> 7 d<24> 43 tms* 79 in0 115 asi<0>/adr<27> 8 d<23> 44 tdi* 80 noncache# 116 irl<3>/irq15 9v ss 45 v ss 81 v ss 117 v ss 10 d<22> 46 tdo 82 adr<2> 118 irl<2>/irq14 11 d<21> 47 out0 83 adr<3> 119 irl<1>/irq13 12 d<20> 48 prsck0 84 adr<4> 120 irl<0>/irq12 13 d<19> 49 error# 85 adr<5> 121 float# 14 d<18> 50 lock# 86 adr<6> 122 pdown# 15 d<17> 51 ctest# 87 adr<7> 123 wkup# 16 d<16> 52 breq# 88 adr<8> 124 reset# 17 btest# 53 pbreq# 89 adr<9> 125 idleen 18 v dd5 54 v dd5 90 v dd5 126 v dd5 19 v ss 55 v ss 91 v ss 127 v ss 20 d<15> 56 bgrnt# 92 adr<10> 128 clksel2 21 d<14> 57 bmack# 93 adr<11> 129 clksel1 22 d<13> 58 bmreq# 94 adr<12> 130 clksel0 23 d<12> 59 ovf# 95 adr<13> 131 clkext 24 d<11> 60 samepage# 96 adr<14> 132 clkin 25 d<10> 61 as# 97 adr<15> 133 irq11 26 d<9> 62 rdwr# 98 adr<16> 134 irq10 27 d<8> 63 rdyout# 99 adr<17> 135 irq9 28 bmode8# 64 cs5# 100 ready# 136 irq8 29 v dd3 65 v dd3 101 v dd3 137 v dd3 30 v ss 66 v ss 102 v ss 138 v ss 31 d<7> 67 cs4# 103 adr<18> 139 reserved 32 d<6> 68 cs3# 104 adr<19> 140 asisel 33 d<5> 69 cs2# 105 adr<20> 141 d<31> 34 d<4> 70 cs1# 106 adr<21> 142 d<30> 35 d<3> 71 cs0# 107 adr<22> 143 d<29> 36 v dd5 72 v dd5 108 v dd5 144 v dd5
mb86830 series 10 n pin description 1. cpu core related pins (continued) symbol pin name i/o function clkin clock i clock input pin. the clock regulates external bus operation.the bus ac characteristics are determined based on the clock. clkext external clock bypass i external clock select pin. the l level at this pin selects the clock signal generated by the internal pll circuit; thech level selects the external clock signal (input through the clkin pin) as it is.fix this pin usually at the l level. reset# system reset i reset input. the l input to this pin initializes the cpu. clksel0 clksel1 clksel2 internal clock select i internal clock setting pins. these pins are used to set the iu (integer unit) and cache operating clock frequencies to x1, x2, x3, x4, or x5 of the external clock frequency. any other setting is prohibited. asisel address space identi- fiers select i asi select signal this pin selects the asi or adr pin. setting this pin to l prohibits the l input to the as# pin in the bus grant state. on the mb86832, this pin is pulled up with a resistor of about 50 k w . ctest# btest# ctest btest i test pins. fix these pins usually to the h level. adr<27:2> or adr<23:2> (mb86833/ 835/836) address bus i/o address pin. the adr<27:2>pin (adr<23:2>pin on the mb86833/835/836)handles the signal for identifying an instruction address or data address.for us- ing the 8/16-bit bus width, adr<1> and adr<0> are output multiplexed with be2# and be3#, respectively.this pin remains enabled during the bus cycle; the value output during the idle cycle is not guaranteed. in the bus grant state, the pin serves as an input used, e.g., by the cs generator circuit (while the l input to the as# pin is prohibited with the asisel pin at the l level) and adr<31:28> (adr<31:24> on the mb86833/835/836) is handled internally as 0. clksel2 clksel1 clksel0 internal clock hll 1 hlh 2 hhl 3 hhh 4 lhh 5 asisel mb86832/834 asi<3:0>/adr<28:31> mb86833/835/836 asi<3:0>/adr<24:27> l adr<28:31> adr<24:27> h asi<3:0> asi<3:0>
mb86830 series 11 (continued) (continued) symbol pin name i/o function d<31:0> data bus i/o data bus signal. this pin provides a bidirectional data bus used for instruction fetch, data load, and data store operations. instructions and word data must be aligned at addresses which are multiples of the number 4. half words and double words must be aligned at addresses which are multiples of the numbers 2 and 8, respectively. d<7:0> and d<15:0> are used in the 8-bit and 16-bit bus modes, respectively. for use in the 16-bit bus mode, a pull-up resistor must be connected to the data bus which is not used (d<31:8> for the 8-bit bus and d<31:16> for the 16- bit bus). as# address strobe i/o address strobe signal. this pin outputs the l level signal for the first bus cycle. basically, the bus cycle starts with the as# signal asserted and ends up with the ready# or rdyout# signal asserted. in the bus grant state, the pin serves as an input used for the signals to actuate the cs generator and wait state generator circuits. rdwr# read/write bus transaction i/o read/write signal. this pin outputs the l level signal when the current bus cycle is the write cycle or the h level signal when it is the read or idle cycle. the output level remains at h orl during the entire bus cycle from the be- ginning to end. in the bus grant state, the pin serves as an input used for generating the dwe0#-dwe3# and doe# signals to enable the dram controller. the signal at this pin is not used when the dram controller is disabled. be0# be1# be2# be3# byte enable o o i/o o bye enable signals. these pins are used to indicate the bytes valid for in write mode when the 32-bit bus width is used. in read mode, all of the be0# to be3# signals are asserted regardless of the data type. for the 8-bit or 16-bit bus width, the be2# and be3# pins output adr<1> and adr<0>, respectively. the be0# to be3# pins remain enabled during the bus cycle; the out- put level during the idle cycle is not guaranteed. in the bus grant state, the pins enter the high-z state and, only when the dram controller is on with the 16-bit bus width used, the be2# pin serves as the adr<1> input pin. (continued) width of bus access type be0# be1# be2# be3# width of 32-bits bus write byte-0 (d<31:24>) * 0 1 1 1 byte-1 (d<23:16>) 1 0 1 1 byte-2 (d<15:8>) 1 1 0 1 byte-3 (d<7:0>) 1 1 1 0 half word-0(d<31:16>) 0 0 1 1 half word-1(d<15:0>) 1 1 0 0 word 0000 read all data types 0 0 0 0
mb86830 series 12 (continued) (continued) symbol pin name i/o function be0# be1# be2# be3# byte enable o o i/o o cs0# cs1# cs2# cs3# cs4# cs5# chip select o chip select signals. these chip select signals are asserted when the address range spec- ifier register (arsr) and address mask register (amr) is accessed with the cs enable bit (bit 4) in the system support control register (sscr) set to 1. (note, however, that only the cs0# pin is indepen- dent of the cs enable bit.) (continued) * : the mark such as (d<31:24>) shows the bit of the data bus used. width of bus access type be0# be1# be2# be3# width of 16-bits bus write byte-0 (d<15:8>) 1 0 0 0 byte-1 (d<7:0>) 0 1 0 0 byte-2 (d<15:8>) 1 0 1 0 byte-3 (d<7:0>) 0 1 1 0 half word-0 (d<15:0>) 0 0 0 0 half word-1 (d<15:0>) 0 0 1 0 word (d<15:0>) access-0 0 0 1 0 word (d<15:0> )access-1 0 0 0 0 read access-0 0 0 0 0 access-1 0 0 1 0 width of 8-bits bus write byte-0 x x 0 0 byte-1 x x 0 1 byte-2 x x 1 0 byte-3 x x 1 1 half word-0 access-1 x x 0 1 half word-0 access-0 x x 0 0 half word-1 access-0 x x 1 1 half word-1 access-1 x x 1 0 word access-0 x x 1 1 word access-1 x x 1 0 word access-2 x x 0 1 word access-3 x x 0 0 read access-0 x x 0 0 access-1 x x 0 1 access-2 x x 1 0 access-3 x x 1 1
mb86830 series 13 (continued) (continued) symbol pin name i/o function breq# bus request i bus request signal. when the breq# signal is asserted by external bus mastering, the cpu releases the bus as shown below upon termination of the current bus cycle: (1)when executing the atomic load store instruction, the cpu releas- es the bus after completing both of loading and storing. (2)when loading or storing a double word: if the breq# signal is asserted at the first word, the cpu releases the bus after transfer of the first word. if the breq# signal is assert- ed in the bus cycle for the second word, the cpu releases the bus after transfer of the second word. (3)when storing data at the 8/16-bit bus width: the cpu releases the bus after transfer of that size of data which is handled by the instruction (for example, after writing 8-bit data four times when storing word data using an 8-bit bus). (4)when loading data at the 8/16-bit bus width: the cpu releases the bus after transfer of one word. when the asisel pin is at the l level, the l input to the as# pin is prohibited in the bus grant state. bgrnt# bus grant o bus grant signal. upon reception of a bus request (breq#), the bgrnt# signal is as- serted to notify the external device of the bus released status. irl3 irl2 irl1 irl0 interrupt re- quest level i interrupt input pins. these pins are used to input an encoded interrupt level. they handle a group of asynchronous input signals, notifying the iu (integer unit) of an interrupt level only when the same level is detected twice at the fall of an external clock pulse. irl = 0000 2 and irl = 1111 (2) indicate no interrupt and a nonmaskable interrupt as defined in the sparc archi- tecture. irl must be determined for priority by an external circuit and must be held until confirmed by the cpu. ready# external ready i ready signal input pin. input the l level signal to upon completion of a bus cycle. upon reception of ready#=l, the cpu starts the next bus cycle. note, however, that thel input to this pin is not necessary when the internal wait state generator circuit is used. for burst transfer, instruction fetch or data load using an 8-bit bus, in- struction fetch or data load using an 16-bit bus, the pin must input the ready signal for the prescribed number of times whenever the address strobe signal is asserted. mexc# memory exception i memory access exception pin. if this pin inputs the l level signal in the same cycle as the ready sig- nal input, the cpu handles it as an instruction access or data access exception to generate a trap. the operation of the device is unpredict- able if the mexc# signal is asserted at a timing other than the same cycle as the ready signal input. (an exception occurring with the psr et bit set to 0 results in an error state.)
mb86830 series 14 (continued) (continued) symbol pin name i/o function error# error signal o error signal. this pin outputs an error signal indicating that the cpu has stopped in the error state resulting from a trap occurring with traps disabled. the cpu can exit the error state only by a reset. asi<3:0> address space identifiers i/o asi pin (address space identification signal) or adr pin. setting the asisel pin to h selects the asi pin; setting it to l selects the adr<28:31> pin on the mb86832/834 or adr<24:27> pin on the mb86833/835/836. when the asisel pin is set to l, the l input to the as# pin is prohibited. a choice of these pins is supported by the mb8682/833/834/835/836 but not by the mb86831-66/80 (only asi<3:0> is available). like the adr<27:2> pin (adr<23:2> pin on the mb86833/835/836), this pin remains enabled for output during the bus cycle. the asi pin serves as an input in the bus grant state, used for cs generation and internal resource address decoding. when asi<3:0> is input from an external device, asi<7:4> is handled as 0 in the cpu. lock# bus lock o bus lock signal. during execution of the atomic load store instruction, the cpu asserts the lock# signal to indicate that the current bus transaction requires multiple transfers which cannot be divided. at a bus request (breq#) during execution of an atomic instruction, the cpu releases the bus (by asserting the bgrnt# signal) upon completion of the instruction exe- cution. for normal use (where bus access permission is controlled by breq#/bgrnt#), the lock# signal need not be used. rdyout# ready output o ready signal output. this pin outputs the composite signal consisting of the ready signal generated by the internal wait state generator circuit and the external ready signal (ready#). while the delay of the internally generated ready signal is regulated based on the clock input, the input from the pin is output delayed as it is at the timing of generation of the external ready signal. idleen idle enable i idle insertion enable pin. if the cycle that follows access to the cs0# area is load or store oper- ation when this pin is at the h level, the cpu starts the next bus cycle after inserting two idle clock cycles. this is efficient when eprom which takes long data bus output off time is connected directly to the cpu.when this pin is at the l level, the cpu inserts only one idle cy- cle before a write cycle immediately after a read cycle (this control is compatible with conventional sparclite processors). fix this pin at the h or l level. bmode8# bmode16# boot mode 8 boot mode 16 i cs0# area bus width setting signals. these pins input signals at a reset to determine the bus width of the cs0# area. setting the bmode8# pin to l selects the 8-bit bus mode; setting the bmode16# pin to l selects the 16-bit bus mode. (the bus width for the cs1#-cs5# area is specified by the bus width/ cacheable control register (bwcr).) fix these pins to l or h. however, it is not allowed to set both of them to l.
mb86830 series 15 (continued) (continued) symbol pin name i/o function noncache# non-cache- able i non-cacheable signal. this pin inputs the signal for exclusion from data caching. the non- cache# signal is enabled by setting the cacheability enable bit (bit 7) in the cache/biu control register (cbir). the l input to this pin when data is read prevents the data and its address from being written to the data cache (the noncache# signal is disabled at an instruction fetch). usually, the noncache# signal must be asserted in the cycle in which the address strobe signal is asserted. even if the non- cache# signal is asserted after a delay of one or more cycles, how- ever, the signal can be used by setting the non-cacheable bit (bit 9, bit 8) in the cache/biu control register (cbir). pdown# power down o sleep mode (low power consumption mode) output pin. l level input to this pin releases the cpu from the sleep mode (low power consumption mode) to start operation. although the pin is an asynchronous input, it requires an l width of at least two clock cycles. input l to this pin only when the pdown# pin is at the l level. wkup# wake-up i sleep mode (low power consumption mode) cancel pin. l input to this pin cancels the cpu sleep mode (low power consump- tion mode), causing the cpu to start operation. although the pin is an asynchronous input, it requires an l width of at least two clock cycles. input thel signal to this pin only when pdown# is l. when pdown# goes h, set this pin to "h". bmreq# burst mode request o burst transfer request pin. if a cache miss occurs when the instruction burst enable bit or data burst enable bit in the bus control register (bcr) has been set, the cpu sets the bmreq# signal to l and requests external memory for burst transfer. the bmreq# signal is also asserted when the dram burst enable bit in the system support control register (sscr) has been set. in this case, however, the external device need not return the bmack# signal because the internal dram controller responds to the request. bmack# burst mode acknowl- edge i burst mode acknowledge input. when a burst transfer request is issued, the burst transfer mode is es- tablished if the l level asserted until the same cycle as the ready# signal is input to this pin. (it is also established either when the l level is input in the same cycle as the ready# signal or when the l level input in an earlier cycle continues until the same cycle as the ready# signal.) when the dram burst enable bit in the system support con- trol register (sscr) has been set, the burst transfer mode is estab- lished even though this pin receives the bmack# signal. pbreq# processor bus request o processor bus request signal. when the cpu requires accessing an external bus the pbreq# signal is asserted to issue a processor bus request to the external bus master when the cpu requires accessing an external bus (when it requires external access after a cache miss) while the cpu has relinquished bus access permission.
mb86830 series 16 (continued) ? state of pins o (v) :the circuit is active with the output at a valid level. o (x) :the circuit is inactive with the output indeterminate. o (z) :output pins and high-z. o (h) :the hlevel is output. o (l) :the l level is output. i (z) :input pins and high-z i (d) :when the dram controller has been enabled, the pin is switched to serve as an output, from the clock cycle that follows the clock cycle in which the as# pin becomes l, and remains as the output until the ready signal input pin becomes l. when the dram controller has been disabled, the pin enters the high-z state. symbol pin name i/o function ovf# timer over- flow o timer overflow signal. this pin outputs the l pulse when the timer reaches 0 after starting counting according to the settings in the dram refresh timer register and dram refresh timer pre-load register with the timer on/off bit in the system support control register (sscr) set to 1 the pulse width is the 1-clock width of the external bus clock when bit 31 in the dram refresh timer pre-load register is 0. when the bit is 1, the pulse width is the 3-clock width. the timer performs counting based on the external bus clock. although this pin is used usually for the dram refresh request signal, it can be connected to the interrupt input (irqx) of the interrupt control- ler (irc) when the pulse width has been specified as the 3-clock width. samepage# same page detect o same-page detection output pin. when the same-page enable bit in the system support control reg- ister (sscr) has been 1, this pin outputs thel level if the cs4# pin is at the l level and if the address masked by the same-page mask register (spgmr) matches the previously accessed address when compared. the samepage# signal remains output during the bus cycle. float# floating i pin float input. fixing this pin at the l level puts all of the output pins and bidirectional pins to the high-z state. pin symbol at reset at bus grant pin symbol at reset at bus grant adr<27:2> o (x) i (d) d<31:0> i (z) i (z) as# o (h) i (z) rdwr# o (h) i (z) be0# o (x) o (z) be1# o (x) o (z) be2# o (x) i (z) be3# o (x) o (z) cs0# to cs5# o (h) o (v) bgrnt# o (h) o (l) error# o (h) o (v) asi<3:0> o (x) i (z) lock# o (h) o (z) rdyout# o (v) o (v) pdown# o (h) o (h) bmreq# o (h) o (h) pbreq# o (h) o (v) ovf# o (h) o (v) samepage# o (h) o (v)
mb86830 series 17 2. dram controller related pins (mb86831/832/833/834/835) ? state of pins o (v) : the circuit is active with the output at a valid level. o (x) : the circuit is inactive with the output indeterminate. o (h) : the h level is output. i (d) : when the dram controller has been enabled, the pin is switched to serve as an output, from the clock cycle that follows the clock cycle in which the as# pin becomes l, and remains as the output until the ready signal input pin becomes l. when the dram controller has been disabled, the pin enters the high-z state. symbol pin name i/o function ras0# ras1# ras2# ras3# dram row address strobe o dram controller ras outputs. the ras0# to ras3# signals are control signals corresponding to dram banks 0 to 3, respectively. the mb86833/835 does not support banks 1 to 3 because the ras1# to ras3# pins do not exist on the chip. cas0# cas1# cas2# cas3# dram column address strobe o dram cas control outputs. for using the 32-bit bus width along with 2-cas dram, the cas0# to cas3# pins are controlled in association with byte 0 (b31 to b24), byte 1 (b23 to b16), byte 2 (b15 to b8), and byte 3 (b7 to b0), respectively. for using the 16-bit bus width along with 2-cas dram, the cas2# and cas3# pins correspond to byte 0 (byte data at an even-numbered ad- dress) and byte 1 (byte data at an odd-numbered address), respective- ly. when the 16-bit bus width is used, the outputs from the cas0# and cas1# pins are unpredictable. when 2-we dram is used, the cas0# to cas3# pins provide the same output. dwe0# dwe1# dwe2# dwe3# dram write enable o dram write enable control outputs. for using 2-we dram, the dwe0# to dwe3# signals are controlled in association with byte 0 (b31 to b24), byte 1 (b23 to b16), byte 2 (b15 to b8), and byte 3 (b7 to b0), respectively. when 2-cas dram is used, the dwe0# to dwe3# pins provide the same output. the dwe1# to dwe3# pins do not exist on the mb86833/835. doe# dram output o dram oe control output. when fast-page dram is used, the dram can be controlled without using the doe# signal because the dwex# and casx# pins are con- trolled at the early write timing. when edo (hyper page mode) dram is used, the doe# signal is required for high-impedance control of the dram output. adr<13:2> address bus i/o dram address signal. the dram controller outputs the multiplexed row and column address- es to a cpu address pin of adr<13:2>. pin symbol at reset at bus grant pin symbol at reset at bus grant ras3# to ras0# o (h) o (v) cas3# to cas0# o (h) o (v) doe# o (h) o (v) adr<13:2> o (x) i (d)
mb86830 series 18 3. interrupt controller (irc) related pins 4. signals for the general-purpose 16-bit timer (mb86836) ? pin status note : o (l) : output l level o (v) : circuit activated ; effective level is output symbol pin name i/o function irq15/irl3 irq14/irl2 irq13/irl1 irq12/irl0 irq11 irq10 irq9 irq8 interrupt request i interrupt input pins. when the active level set for the interrupt controller (irc) trigger mode is input to these pins, the request sense register of the interrupt control- ler (irc) holds the interrupt request. (the interrupt controller (irc) evaluates priority levels and performs coding for the irl<3:0> pin, and notifies the cpu core of the interrupt level.) the irq15 to irq12 signals are assigned to the irl<3:0> pin. they function as irq15 to irq12 when the interrupt controller (irc) be- comes enabled. symbol pin name i/o function prsck0 prescaler clock output0 o prescaler output pin. the external clock mode is not supported, which is included in the functions of the prescaler on the mb86942. the pin is reset to l. out0 timer output0 o timer output pin. the external clock mode is not supported, which is included in the functions of the timer on the mb86942. the pin is reset to l. in0 timer input0 i timer count operation control pin. this pin inputs the gate signal in mode0 to mode3 and the external trigger signal in mode4.this pin has an internal pull-down resistor. symbol reset bus granted prsck0 o (l) o (v) out0 o (l) o (v)
mb86830 series 19 5. ddsu (debug support unit) related pins (mb86832/834) 6. signals for the jtag test port (mb86836) symbol pin name i/o function emubrk# emulator break i emulator break pin. when a reset is canceled, the emubrk# signal level is input to set a mode in combination with the emueng# signal level. the mb86832 contains a pull-up resistor (about 50 k w ). leave this pin open when the dsu (debug support unit) is not used. the mb86834 has no pull-up resistor. emuenb# emulator enable i/o emulator enable pin. when a reset is canceled, the emuenb# signal level is input to set a mode in combination with the emubrk# signal level. when a reset is canceled, this pin becomes an output pin after four clock cycles if either (dsubrk# = dsuenb# = l) or (dsubrk# = h, dsuenb# = l) is set. the mb86832 contains a pull-up resistor (about 50 k w ). leave this pin open when the dsu (debug support unit) is not used. the mb86834 has no pull-up resistor. emud<3:0> emulator data bus i/o emulator data pin. this pin outputs traced instruction addresses divided into eight compo- nents in the monitor mode. it also inputs instruction codes and outputs instruction or data addresses in the dsu mode. since this pin serves as an output with the dsu disabled, leave the pin open if the dsu (debug support unit) is not to be used. emusd<3:0> emulator status/ data bus i/o emulator status/data pin. this pin outputs the cpu status in the monitor mode and. it also inputs instruction codes and outputs instruction or data addresses in the dsu mode. since this pin serves as an output with the dsu disabled, leave the pin open if the dsu (debug support unit) is not to be used. symbol pin name i/o function tck test clock i jtag test clock input pin. this pin has an internal pull-down resistor. tms test mode i jtag test mode selection pin. this pin has an internal pull-down resistor. tdi test data in i jtag test data input pin. this pin has an internal pull-down resistor. tdo test data out o jtag test data output pin. trst# test reset i jtag test reset pin. this pin is reset to l. it has an internal pull-down resistor.
mb86830 series 20 n block diagram *1:the cache capacity is as follows. *2:dsu (debug support unit) is added with mb86832/834. parts number item mb86831 mb86832 mb86833 mb86834 MB86835 mb86836 instruction cash 4 kb/2 way 8 kb/2 way 1 kb/direct 16 kb/2 way 4 kb/2 way 8 kb/2 way data cash 2 kb/2 way 8 kb/2 way 1 kb/direct 16 kb/2 way 2 kb/2 way 8 kb/2 way divide step multiply sparc integer unit instruction cache 1 cpu core data cache 1 clock generator clkin peripheral resource bus interface unit data address decode wait state generator dram support 16 bit timer x1 x2 x3 x4 x5 scan i data 32 i address 32 d address 32 d data 32 address asi control irl chip_sel page_det refresh debug support unit 2
mb86830 series 21 n electric characteristics 1. absolute maximum ratings (1)mb86831-66/mb86832-66/mb86833 (v ss = 0.0 v) (2)mb86834-108,-120/mb86836-90,-108 (v ss = 0.0 v) (3)MB86835 (v ss = 0.0 v) parameter symbol rating unit min. max. power supply voltage(i/o) v dd5 - 0.5 6 v power supply voltage(internal) v dd3 - 0.5 4 v input voltage v i - 0.5 v dd5 + 0.5 v storage temperature t stg - 55 + 125 c temperature at bias t bias 0 + 70 c overshoot ? within v dd5 + 1.0 v (within 50 ns ) ? undershoot ? within v ss - 1.0 v (within 50 ns ) ? parameter symbol rating unit min. max. power supply voltage(i/o) v dd5 (v dde ) - 0.5 4.0 v power supply voltage(internal) v dd3 (v ddi ) - 0.5 3.0 v input voltage v i - 0.5 v dde + 0.5 v storage temperature t stg - 55 + 125 c temperature at bias t bias 0 + 70 c parameter symbol rating unit min. max. power supply voltage(i/o) v dd5 - 0.5 4 v power supply voltage(internal) v dd3 - 0.5 4 v input voltage v i - 0.5 v dd5 + 0.5 v storage temperature t stg - 55 + 125 c temperature at bias t bias 0 + 70 c overshoot ? within v dd5 + 1.0 v (within 50 ns ) ? undershoot ? within v ss - 1.0 v (within 50 ns ) ?
mb86830 series 22 (notes on board wiring) ? for connecting the power supply and ground (gnd), use multiple v dd and v ss pins. the system board based on the mb86830 series must be a multilayer board containing power supply (v dd ) and gnd (v ss ) layers for stable power supply. leave any pin designated as n.c. unconnected. ? insert sufficient decoupling capacitors near the mb86830 series. changes to the output levels of many of the output pins on the mb86830 series (in particular, those with large load capacitance) may cause variation in power supply. ? for those systems which run at a high frequency, low-inductance capacitors and mutual wiring are recom- mended. inductance can be lowered by shortening the distance between the processor and decoupling capacitor. ? for system reliability, the pin entering the tristate when the mb86830 series enters the bus grant state should be driven by a bus master. in particular, the lock#, adr<27:2>, asi<3:0> (asi<3:0>/adr<28:31>, asi<3:0> /adr<24:27>), be0# to be3#, d<31:0>, as#, and rdwr# pins must be driven by other bus masters. usually, these pins require no external pull-up resistor because they are driven by the processor when the processor is active or idle. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current,temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings.
mb86830 series 23 2. recommended operating conditions (1)mb86831-66/mb86832-66/mb86833 (v ss = 0.0 v) (2)mb86831-80/mb86832- 80, -100 (v ss = 0.0 v) (3)mb86834-108,-120/mb86836-90,-108 (v ss = 0.0 v) parameter symbol value unit min. typ. max. power supply voltage (i/o = 5.0 v) v dd5 4.75 5.0 5.25 v power supply voltage (i/o = 3.3 v) v dd5 3.0 3.3 3.6 v power supply voltage (internal) v dd3 3.0 3.3 3.6 v l level input voltage v il 0 ? v dd3 0.25 v h level input voltage v ih v dd3 0.65 ? v dd5 v operating temperature topr 0 + 25 + 70 c parameter symbol value unit min. typ. max. power supply voltage (i/o = 5.0 v) v dd5 4.75 5.0 5.25 v power supply voltage (i/o = 3.3 v) v dd5 3.15 3.3 3.45 v power supply voltage (internal) v dd3 3.15 3.3 3.45 v l level input voltage v il 0 ? v dd3 0.25 v h level input voltage v ih v dd3 0.65 ? v dd5 v operating temperature topr 0 + 25 + 70 c parameter symbol value unit min. typ. max. power supply voltage (i/o) v dd5 (v dde ) 3.15 3.3 3.45 v power supply voltage (internal) v dd3 (v dde )2.4 2.5 2.6 v l level input voltage v il - 0.3 ? 0.8 v h level input voltage v ih 2.0 ? v dde + 0.3 v operating temperature topr 0 + 25 + 70 c
mb86830 series 24 (4)MB86835 (v ss = 0.0 v) ? the mb86831/832/833 can be used with a 5.0-v or 3.3-v interface. 5.0-v interface: v dd5 = 5.0 v, v dd3 = 3.3 v (two power supplies) 3.3-v interface: v dd5 = v dd3 = 3.3 v (single power supply) ? when the 3.3-v interface is used, all signals input to the mb86830 series must be 3.3 v because the mb86830 series cannot input 5.0-v signals with that interface. ? when the 5.0-v interface is used, the output fully swings at 5.0 v. although the input is always defined by a 3.3-v power supply, it can also accept 3.3 v or more. ? when the 5.0-v interface is used, the mb86830 series requires two power supplies. follow the procedures below to turn on and off these power supplies: power-on procedure: v dd3 ? v dd5 ? signal shutdown procedure: signal ? v dd5 ? v dd3 ? the mb86834/836 requires two power supplies of v dde (3.3-v system) and v ddi (2.5-v system). follow the procedures below to turn on and off these power supplies: power-on procedure: v ddi ? v dde ? signal shutdown procedure: signal ? v dde ? v ddi ? the MB86835 has two v dd , v dd3 and v dd5 . connect each of them to a 3.3-v power supply. ? the mb86834/835/836 uses only a 3.3-v interface; they cannot accept 5-v signals. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit min. typ. max. power supply voltage (i/o = 3.3 v) v dd5 3.15 3.3 3.45 v power supply voltage (internal) v dd3 3.15 3.3 3.45 v l level input voltage v il 0 ? v dd3 0.25 v h level input voltage v ih v dd3 0.65 ? v dd5 v operating temperature topr 0 + 25 + 70 c
mb86830 series 25 3. dc characteristics (1)mb86831-66 (maximum internal operation frequency:66 mhz) ? 5.0 v interface (v dd5 = 5.0 v 5 % , v dd3 = 3.3 v 0.3 v, v ss = 0.0 v, t a = 0 c to + 70 c) ? 3.3 v interface (v dd5 = v dd3 = 3.3 v 0.3 % , v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? v dd3 0.25 v h level input voltage v ih ? v dd3 0.65 ? v dd5 v l level output voltage v ol i ol = 4 ma 0 ? 0.4 v h level output voltage v oh i oh = - 4 ma v dd5 - 0.5 ? v dd5 v input leakage current i li v in = 0 or v dd5 - 10 ? 10 m a trial state output leakage current i lz v out = 0 or v dd5 - 10 ? 10 m a power supply current (v dd5 )i dd 33 mhz no-load ? 40 ? ma power supply current (v dd3 )i dd 66 mhz ? 150 ? ma at sleep power supply current(v dd3 ) i sleep 66 mhz ? 15 ? ma capacity of pins c pin v dd5 = v i = 0 f = 1 mhz ?? 16 pf parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? v dd3 0.25 v h level input voltage v ih ? v dd3 0.65 ? v dd5 v l level output voltage v ol i ol = 2 ma 0 ? 0.4 v h level output voltage v oh i oh = - 2 ma v dd5 - 0.5 ? v dd5 v input leakage current i li v in = 0 or v dd5 - 10 ? 10 m a trial state output leakage current i lz v out = 0 or v dd5 - 10 ? 10 m a power supply current (v dd5 )i dd 33 mhz no-load ? 30 ? ma power supply current (v dd3 )i dd 66 mhz ? 150 ? ma at sleep power supply current(v dd3 ) i sleep 66 mhz ? 15 ? ma capacity of pins c pin v dd5 = v i = 0 f = 1 mhz ?? 16 pf
mb86830 series 26 (2)mb86831-80 (maximum internal operation frequency:80 mhz) ? 5.0 v interface (v dd5 = 5.0 v 5 % , v dd3 = 3.3 v 0.15 v, v ss = 0.0 v, t a = 0 c to + 70 c) ? 3.3 v interface (v dd5 = 5.0 v 5 % , v dd3 = 3.3 v 0.15 v, v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? v dd3 0.25 v h level input voltage v ih ? v dd3 0.65 ? v dd5 v l level output voltage v ol i ol = 4 ma 0 ? 0.4 v h level output voltage v oh i oh = - 4 ma v dd5 - 0.5 ? v dd5 v input leakage current i li v in = 0 or v dd5 - 10 ? 10 m a trial state output leakage current i lz v out = 0 or v dd5 - 10 ? 10 m a power supply current (v dd5 )i dd 40mhz no-load ? 50 ? ma power supply current (v dd3 )i dd 80mhz ? 200 ? ma at sleep power supply current(v dd3 ) i sleep 80mhz ? 20 ? ma capacity of pins c pin v dd5 = v i = 0 f = 1 mhz ?? 16 pf parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? v dd3 0.25 v h level input voltage v ih ? v dd3 0.65 ? v dd5 v l level output voltage v ol i ol = 2 ma 0 ? 0.4 v h level output voltage v oh i oh = - 2 ma v dd5 - 0.5 ? v dd5 v input leakage current i li v in = 0 or v dd5 - 10 ? 10 m a trial state output leakage current i lz v out = 0 or v dd5 - 10 ? 10 m a power supply current (v dd5 )i dd 40mhz no-load ? 36 ? ma power supply current (v dd3 )i dd 80mhz ? 200 ? ma at sleep power supply current(v dd3 ) i sleep 80mhz ? 20 ? ma capacity of pins c pin v dd5 = v i = 0 f = 1 mhz ?? 16 pf
mb86830 series 27 (3)mb86832-66 (maximum internal operation frequency:66 mhz) ? 5.0 v interface (v dd5 = 5.0 v 5 % , v dd3 = 3.3 v 0.3 v, v ss = 0.0 v, t a = 0 c to + 70 c) ? 3.3 v interface (v dd5 = v dd3 = 3.3 v 0.3 v, v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? v dd3 0.25 v h level input voltage v ih ? v dd3 0.65 ? v dd5 v l level output voltage v ol i ol = 4 ma 0 ? 0.4 v h level output voltage v oh i oh = - 4 ma v dd5 - 0.5 ? v dd5 v input leakage current i li v in = 0 or v dd5 - 10 ? 10 m a trial state output leakage current i lz v out = 0 or v dd5 - 10 ? 10 m a power supply current (v dd5 )i dd 33 mhz no-load ? 40 ? ma power supply current (v dd3 )i dd 66 mhz ? 200 ? ma at sleep power supply current(v dd3 ) i sleep 66 mhz ? 15 ? ma capacity of pins c pin v dd5 = v i = 0 f = 1 mhz ?? 16 pf parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? v dd3 0.25 v h level input voltage v ih ? v dd3 0.65 ? v dd5 v l level output voltage v ol i ol = 2 ma 0 ? 0.4 v h level output voltage v oh i oh = - 2 ma v dd5 - 0.5 ? v dd5 v input leakage current i li v in = 0 or v dd5 - 10 ? 10 m a trial state output leakage current i lz v out = 0 or v dd5 - 10 ? 10 m a power supply current (v dd5 )i dd 33 mhz no-load ? 30 ? ma power supply current (v dd3 )i dd 66 mhz ? 200 ? ma at sleep power supply current(v dd3 ) i sleep 66 mhz ? 15 ? ma capacity of pins c pin v dd5 = v i = 0 f = 1 mhz ?? 16 pf
mb86830 series 28 (4)mb86832-80 (maximum internal operation frequency:80 mhz) ? 5.0 v interface (v dd5 = 5.0 v 5 % , v dd3 = 3.3 v 0.15 v, v ss = 0.0 v, t a = 0 c to + 70 c) ? 3.3 v interface (v dd5 = v dd3 = 3.3 v 0.15 v, v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? v dd3 0.25 v h level input voltage v ih ? v dd3 0.65 ? v dd5 v l level output voltage v ol i ol = 4 ma 0 ? 0.4 v h level output voltage v oh i oh = - 4 ma v dd5 - 0.5 ? v dd5 v input leakage current i li v in = 0 or v dd5 - 10 ? 10 m a trial state output leakage current i lz v out = 0 or v dd5 - 10 ? 10 m a power supply current (v dd5 )i dd 40mhz no-load ? 50 ? ma power supply current (v dd3 )i dd 80mhz ? 250 ? ma at sleep power supply current(v dd3 ) i sleep 80mhz ? 20 ? ma capacity of pins c pin v dd5 = v i = 0 f = 1 mhz ?? 16 pf parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? v dd3 0.25 v h level input voltage v ih ? v dd3 0.65 ? v dd5 v l level output voltage v ol i ol = 2 ma 0 ? 0.4 v h level output voltage v oh i oh = - 2 ma v dd5 - 0.5 ? v dd5 v input leakage current i li v in = 0 or v dd5 - 10 ? 10 m a trial state output leakage current i lz v out = 0 or v dd5 - 10 ? 10 m a power supply current (v dd5 )i dd 40mhz no-load ? 36 ? ma power supply current (v dd3 )i dd 80mhz ? 250 ? ma at sleep power supply current(v dd3 ) i sleep 80mhz ? 20 ? ma capacity of pins c pin v dd5 = v i = 0 f = 1 mhz ?? 16 pf
mb86830 series 29 (5)mb86832-100 (maximum internal operation frequency:100 mhz) ? 5.0 v interface (v dd5 = 5.0 v 5 % , v dd3 = 3.3 v 0.15 v, v ss = 0.0 v, t a = 0 c to + 70 c) ? 3.3 v interface (v dd5 = v dd3 = 3.3 v 0.15 v, v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? v dd3 0.25 v h level input voltage v ih ? v dd3 0.65 ? v dd5 v l level output voltage v ol i ol = 4 ma 0 ? 0.4 v h level output voltage v oh i oh = - 4 ma v dd5 - 0.5 ? v dd5 v input leakage current i li v in = 0 or v dd5 - 10 ? 10 m a trial state output leakage current i lz v out = 0 or v dd5 - 10 ? 10 m a power supply current (v dd5 )i dd 33mhz no-load ? 40 ? ma power supply current (v dd3 )i dd 100mhz ? 300 ? ma at sleep power supply current(v dd3 ) i sleep 100mhz ? 25 ? ma capacity of pins c pin v dd5 = v i = 0 f = 1 mhz ?? 16 pf parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? v dd3 0.25 v h level input voltage v ih ? v dd3 0.65 ? v dd5 v l level output voltage v ol i ol = 2 ma 0 ? 0.4 v h level output voltage v oh i oh = - 2 ma v dd5 - 0.5 ? v dd5 v input leakage current i li v in = 0 or v dd5 - 10 ? 10 m a trial state output leakage current i lz v out = 0 or v dd5 - 10 ? 10 m a power supply current (v dd5 )i dd 33mhz no-load ? 30 ? ma power supply current (v dd3 )i dd 100mhz ? 300 ? ma at sleep power supply current(v dd3 ) i sleep 100mhz ? 25 ? ma capacity of pins c pin v dd5 = v i = 0 f = 1 mhz ?? 16 pf
mb86830 series 30 (6)mb86833 (maximum internal operation frequency:66 mhz) ? 5.0 v interface (v dd5 = 5.0 v 5 % , v dd3 = 3.3 v 0.3 v, v ss = 0.0 v, t a = 0 c to + 70 c) ? 3.3 v interface (v dd5 = v dd3 = 3.3 v 0.3 v, v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? v dd3 0.25 v h level input voltage v ih ? v dd3 0.65 ? v dd5 v l level output voltage v ol i ol = 4 ma 0 ? 0.4 v h level output voltage v oh i oh = - 4 ma v dd5 - 0.5 ? v dd5 v input leakage current i li v in = 0 or v dd5 - 10 ? 10 m a trial state output leakage current i lz v out = 0 or v dd5 - 10 ? 10 m a power supply current (v dd5 )i dd 33 mhz no-load ? 40 ? ma power supply current (v dd3 )i dd 66 mhz ? 120 ? ma at sleep power supply current(v dd3 ) i sleep 66 mhz ? 15 ? ma capacity of pins c pin v dd5 = v i = 0 f = 1 mhz ?? 16 pf parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? v dd3 0.25 v h level input voltage v ih ? v dd3 0.65 ? v dd5 v l level output voltage v ol i ol = 2 ma 0 ? 0.4 v h level output voltage v oh i oh = - 2 ma v dd5 - 0.5 ? v dd5 v input leakage current i li v in = 0 or v dd5 - 10 ? 10 m a trial state output leakage current i lz v out = 0 or v dd5 - 10 ? 10 m a power supply current (v dd5 )i dd 33 mhz no-load ? 30 ? ma power supply current (v dd3 )i dd 66 mhz ? 120 ? ma at sleep power supply current(v dd3 ) i sleep 66 mhz ? 15 ? ma capacity of pins c pin v dd5 = v i = 0 f = 1 mhz ?? 16 pf
mb86830 series 31 (7)mb86834-108 (maximum internal operation frequency:108 mhz) (v dd5 = 3.3 v 0.15 v, v dd3 = 2.5 v 0.1 v, v ss = 0.0 v, t a = 0 c to + 70 c) (8)mb86834-120 (maximum internal operation frequency:120 mhz) (v dd5 = 3.3 v 0.15 v, v dd3 = 2.5 v 0.1 v, v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? 0.8 v h level input voltage v ih ? 2.0 ? v dde v l level output voltage v ol i ol = 2.0ma 0 ? 0.4 v h level output voltage v oh i oh = - 2.0ma v dde - 0.4 ? v dde v input leakage current i li v in = 0 or v dde - 5 ? 5 m a trial state output leakage current i lz v out = 0 or v dde - 5 ? 5 m a power supply current (v dd5 )i dd 33 mhz no-load ? 30 ? ma power supply current (v dd3 )i dd 108 mhz ? 250 ? ma at sleep power supply current(v dd3 ) i sleep 108 mhz ? 20 ? ma capacity of pins c pin v dde = v i = 0 f = 1 mhz ?? 16 pf parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? 0.8 v h level input voltage v ih ? 2.0 ? v dde v l level output voltage v ol i ol = 2.0ma 0 ? 0.4 v h level output voltage v oh i oh = - 2.0ma v dde - 0.4 ? v dde v input leakage current i li v in = 0 or v dde - 5 ? 5 m a trial state output leakage current i lz v out = 0 or v dde - 5 ? 5 m a power supply current (v dd5 )i dd 40 mhz no-load ? 36 ? ma power supply current (v dd3 )i dd 120 mhz ? 280 ? ma at sleep power supply current(v dd3 ) i sleep 120 mhz ? 23 ? ma capacity of pins c pin v dde = v i = 0 f = 1 mhz ?? 16 pf
mb86830 series 32 (9)MB86835 (maximum internal operation frequency:84 mhz) (v dd5 = v dd3 = 3.3 v 0.15 v, v ss = 0.0 v, t a = 0 c to + 70 c) (10)mb86836-90 (maximum internal operation frequency:90 mhz) (v dd5 = 3.3 v 0.15 v, v dd3 = 2.5 v 0.1 v, v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? v dd3 0.25 v h level input voltage v ih ? v dd3 0.65 ? v dd5 v l level output voltage v ol i ol = 2 ma 0 ? 0.4 v h level output voltage v oh i oh = - 2 ma v dd5 - 0.5 ? v dd5 v input leakage current i li v in = 0 or v dd5 - 10 ? 10 m a trial state output leakage current i lz v out = 0 or v dd5 - 10 ? 10 m a power supply current (v dd5 + v dd3 ) i dd 84 mhz no-load ? 200 ? ma at sleep power supply current (v dd3 ) i sleep 84 mhz ? 20 ? ma capacity of pins c pin v dd5 = v i = 0 f = 1 mhz ?? 16 pf parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? 0.8 v h level input voltage v ih ? 2.0 ? v dd5 v l level output voltage v ol i ol = 2 ma 0 ? 0.4 v h level output voltage v oh i oh = - 2 ma v dd5 - 0.4 ? v dd5 v input leakage current i li v in = 0 or v dd5 - 5 ? 5 m a trial state output leakage current i lz v out = 0 or v dd5 - 5 ? 5 m a power supply current (v dd5 = 3.3 v) i dd 40 mhz no-load ? 36 ? ma power supply current (v dd3 = 2.5 v) i dd 90 mhz ? 180 ? ma at sleep power supply current i sleep 90 mhz ? 17 ? ma capacity of pins c pin v dd5 = v i = 0 f = 1 mhz ?? 16 pf
mb86830 series 33 (11)mb86836-108 (maximum internal operation frequency:108 mhz) (v dd5 = 3.3 v 0.15 v, v dd3 = 2.5 v 0.1 v, v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol condition value unit min. typ. max. l level input voltage v il ? 0 ? 0.8 v h level input voltage v ih ? 2.0 ? v dd5 v l level output voltage v ol i ol = 2 ma 0 ? 0.4 v h level output voltage v oh i oh = - 2 ma v dd5 - 0.4 ? v dd5 v input leakage current i li v in = 0 or v dd5 - 5 ? 5 m a trial state output leakage current i lz v out = 0 or v dd5 - 5 ? 5 m a power supply current (v dd5 = 3.3 v) i dd 40 mhz no-load ? 36 ? ma power supply current (v dd3 = 2.5 v) i dd 108 mhz ? 200 ? ma at sleep power supply current i sleep 108 mhz ? 20 ? ma capacity of pins c pin v dd5 = v i = 0 f = 1 mhz ?? 16 pf
mb86830 series 34 4. ac characteristics all are provided by clkin (bus clock), and the ac characteristic does not depend on the frequency of the oper- ation in cpu. (1)mb86831-66/mb86832-66/mb86833 (maximum internal operation frequency:66 mhz) (v dd3 = 3.3 v 0.3 v, v ss = 0.0 v, t a = 0 c to + 70 c) (continued) classifica- tion parameter symbol value unit v dd5 = 5.0 v 5 % v dd5 = 3.3 v 0.3 v min. max. min. max. clk clkin cycle time ? 30 100 30 100 ns clkin high time ? 10 ? 10 ? ns clkin low time ? 10 ? 10 ? ns clkin rising time ?? 3 ? 3ns clkin falling time ?? 3 ? 3ns output delay time d<31:0> ? 20 ? 20 ns hold time 2 ? 2 ? ns delay time adr<27:2> ? 20 ? 21 ns hold time 2 ? 2 ? ns delay time be0# to be3# ? 20 ? 21 ns hold time 2 ? 2 ? ns delay time asi<3:0> ? 20 ? 21 ns hold time 2 ? 2 ? ns delay time cs0# to cs5# ? 20 ? 21 ns hold time 2 ? 2 ? ns delay time samepage# ? 20 ? 21 ns hold time 2 ? 2 ? ns delay time rdwr# ? 18 ? 19 ns hold time 2 ? 2 ? ns delay time lock# ? 18 ? 19 ns hold time 2 ? 2 ? ns delay time as# ? 18 ? 19 ns hold time 2 ? 2 ? ns delay time ovf# ? 20 ? 21 ns hold time 2 ? 2 ? ns delay time bgrnt# ? 18 ? 19 ns hold time 2 ? 2 ? ns delay time pbreq# ? 18 ? 19 ns hold time 2 ? 2 ? ns delay time bmreq# ? 18 ? 19 ns hold time 2 ? 2 ? ns
mb86830 series 35 (continued) (v dd3 = 3.3 v 0.3 v, v ss = 0.0 v, t a = 0 c to + 70 c) (continued) classifica- tion parameter symbol value unit v dd5 = 5.0 v 5 % v dd5 = 3.3 v 0.3 v min. max. min. max. output delay time rdyout# (internal ready mode) ? 20 ? 21 ns hold time 2 ? 2 ? ns delay time rdyout# * (external ready mode) ? 15 ? 15 ns hold time 2 ? 2 ? ns delay time error# ? 20 ? 21 ns hold time 2 ? 2 ? ns delay time pdown# ? 20 ? 21 ns hold time 2 ? 2 ? ns input setup time ready# 14 ? 14 ? ns hold time 2 ? 2 ? ns setup time mexc# 14 ? 14 ? ns hold time 2 ? 2 ? ns setup time d<31:0> 14 ? 14 ? ns hold time 2 ? 2 ? ns setup time breq# 12 ? 12 ? ns hold time 2 ? 2 ? ns setup time bmack# 12 ? 12 ? ns hold time 2 ? 2 ? ns setup time irl<3:0> asynchronous asynchronous ns hold time asynchronous asynchronous ns setup time wkup# asynchronous asynchronous ns hold time asynchronous asynchronous ns external bus master input setup time rdwr# 12 ? 12 ? ns hold time 2 ? 2 ? ns setup time as# 12 ? 12 ? ns hold time 2 ? 2 ? ns input setup time asi<3:0> 12 ? 12 ? ns hold time 2 ? 2 ? ns setup time adr<27:2> 12 ? 12 ? ns hold time 2 ? 2 ? ns setup time be2# 12 ? 12 ? ns hold time 2 ? 2 ? ns
mb86830 series 36 (continued) (v dd3 = 3.3 v 0.3 v, v ss = 0.0 v, t a = 0 c to + 70 c) p:period (cycle time) * : rdyout# at the external ready mode is provided for from ready# input. notes ? each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise noted. ? each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v, the input level is 0.4 to 2.4 v, and the input rise time and fall time are 2 ns or less. ? do not leave more than one output pins short-circuited for 1 second or more. ? the external output load capacitance is 30 pf. ? the specifications of pins other than those pins designated as asynchronous inputs and than the rdyout# pin in external ready mode are determined by the rising edge of the external clock (clkin). ? these specifications are subject to change for improvement. ? the reset period requires at least 4 clkin cycles. the pll oscillation stabilization delay time requires at least 4000 clock (clkin) pulses. for 40-mhz (25 ns) clock input, for example, the reset signal must therefore be negated 100 m s later. classifica- tion parameter symbol value unit v dd5 = 5.0 v 5% v dd5 = 3.3 v 0.3 v min. max. min. max. dramc output delay time ras0# to ras3# ? 15 ? 15 ns hold time 2 ? 2 ? ns delay time cas0# to cas3# ? 15 ? 15 ns hold time 2 ? 2 ? ns delay time dwe0# to dwe3# ? 15 ? 15 ns hold time 2 ? 2 ? ns delay time doe# ? 15 ? 15 ns hold time 2 ? 2 ? ns irc input setup time irq15 to irq8 asynchronous asynchronous ns hold time asynchronous asynchronous ns h level period 2 p + 10 ? 2 p + 10 ? ns l level period 2 p + 10 ? 2 p + 10 ? ns
mb86830 series 37 (2)mb86831-80/mb86832-80 (maximum internal operation frequency:80 mhz) (v dd3 = 3.3 v 0.15 v, v ss = 0.0 v, t a = 0 c to + 70 c ) (continued) classifica- tion parameter symbol value unit v dd5 = 5.0 v 5% v dd5 = 3.3 v 0.15 v min. max. min. max. clk clkin cycle time ? 25 100 25 100 ns clkin high time ? 8 ? 8 ? ns clkin low time ? 8 ? 8 ? ns clkin rising time ?? 3 ? 3ns clkin falling time ?? 3 ? 3ns output delay time d<31:0> ? 16 ? 20 ns hold time 2 ? 2 ? ns delay time adr<27:2> ? 18 ? 21 ns hold time 2 ? 2 ? ns delay time be0# to be3# ? 16 ? 21 ns hold time 2 ? 2 ? ns delay time asi<3:0> ? 16 ? 21 ns hold time 2 ? 2 ? ns delay time cs0# to cs5# ? 16 ? 21 ns hold time 2 ? 2 ? ns delay time samepage# ? 16 ? 21 ns hold time 2 ? 2 ? ns delay time rdwr# ? 14 ? 19 ns hold time 2 ? 2 ? ns delay time lock# ? 14 ? 19 ns hold time 2 ? 2 ? ns delay time as# ? 14 ? 19 ns hold time 2 ? 2 ? ns delay time ovf# ? 16 ? 21 ns hold time 2 ? 2 ? ns delay time bgrnt# ? 14 ? 19 ns hold time 2 ? 2 ? ns delay time pbreq# ? 14 ? 19 ns hold time 2 ? 2 ? ns delay time bmreq# ? 16 ? 19 ns hold time 2 ? 2 ? ns delay time rdyout# (internal ready mode) ? 16 ? 21 ns hold time 2 ? 2 ? ns
mb86830 series 38 (continued) (v dd3 = 3.3 v 0.15 v, v ss = 0.0 v, t a = 0 c to + 70 c ) (continued) classifica- tion parameter symbol value unit v dd5 = 5.0 v 5 % v dd5 = 3.3 v 0.15 v min. max. min. max. output delay time rdyout# * (external ready mode) ? 14 ? 15 ns hold time 2 ? 2 ? ns delay time error# ? 14 ? 21 ns hold time 2 ? 2 ? ns delay time pdown# ? 14 ? 21 ns hold time 2 ? 2 ? ns input setup time ready# 10 ? 10 ? ns hold time 2 ? 2 ? ns setup time mexc# 10 ? 10 ? ns hold time 2 ? 2 ? ns setup time d<31:0> 12 ? 12 ? ns hold time 2 ? 2 ? ns setup time breq# 10 ? 10 ? ns hold time 2 ? 2 ? ns setup time bmack# 10 ? 10 ? ns hold time 2 ? 2 ? ns setup time irl<3:0> asynchronous asynchronous ns hold time asynchronous asynchronous ns setup time wkup# asynchronous asynchronous ns hold time asynchronous asynchronous ns external bus master input setup time rdwr# 12 ? 12 ? ns hold time 2 ? 2 ? ns setup time as# 12 ? 12 ? ns hold time 2 ? 2 ? ns input setup time asi<3:0> 12 ? 12 ? ns hold time 2 ? 2 ? ns setup time adr<27:2> 12 ? 12 ? ns hold time 2 ? 2 ? ns setup time be2# 12 ? 12 ? ns hold time 2 ? 2 ? ns
mb86830 series 39 (continued) (v dd3 = 3.3 v 0.15 v, v ss = 0.0 v, t a = 0 c to + 70 c ) p:period (cycle time) * : rdyout# at the external ready mode is provided for from ready# input. notes ? each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise noted. ? each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v, the input level is 0.4 to 2.4 v, and the input rise time and fall time are 2 ns or less. ? do not leave more than one output pins short-circuited for 1 second or more. ? the external output load capacitance is 30 pf. ? the specifications of pins other than those pins designated as asynchronous inputs and than the rdyout# pin in external ready mode are determined by the rising edge of the external clock (clkin). ? these specifications are subject to change for improvement. ? the reset period requires at least 4 clkin cycles. the pll oscillation stabilization delay time requires at least 4000 clock (clkin) pulses. for 40-mhz (25 ns) clock input, for example, the reset signal must therefore be negated 100 m s later. classifica- tion parameter symbol value unit v dd5 = 5.0 v 5 % v dd5 = 3.3 v 0.15 v min. max. min. max. dramc output delay time ras0# to ras3# ? 12 ? 15 ns hold time 2 ? 2 ? ns delay time cas0# to cas3# ? 12 ? 15 ns hold time 2 ? 2 ? ns delay time dwe0# to dwe3# ? 12 ? 15 ns hold time 2 ? 2 ? ns delay time doe# ? 12 ? 15 ns hold time 2 ? 2 ? ns irc input setup time irq15 to irq8 asynchronous asynchronous ns hold time asynchronous asynchronous ns h level period 2 p + 10 ? 2 p + 10 ? ns l level period 2 p + 10 ? 2 p + 10 ? ns
mb86830 series 40 (3)mb86832-100 (maximum internal operation frequency:100 mhz) (v dd3 = 3.3 v 0.15 v, v ss = 0.0 v, t a = 0 c to + 70 c) (continued) classifica- tion parameter symbol value unit v dd5 = 5.0 v 5% v dd5 = 3.3 v 0.15 v min. max. min. max. clk clkin cycle time ? 25 100 25 100 ns clkin high time ? 10 ? 10 ? ns clkin low time ? 10 ? 10 ? ns clkin rising time ?? 3 ? 3ns clkin falling time ?? 3 ? 3ns output delay time d<31:0> ? 16 ? 20 ns hold time 2 ? 2 ? ns delay time adr<27:2> ? 18 ? 21 ns hold time 2 ? 2 ? ns delay time be0# to be3# ? 16 ? 21 ns hold time 2 ? 2 ? ns delay time asi<3:0> ? 16 ? 21 ns hold time 2 ? 2 ? ns delay time cs0# to cs5# ? 16 ? 21 ns hold time 2 ? 2 ? ns delay time samepage# ? 16 ? 21 ns hold time 2 ? 2 ? ns delay time rdwr# ? 14 ? 19 ns hold time 2 ? 2 ? ns delay time lock# ? 14 ? 19 ns hold time 2 ? 2 ? ns delay time as# ? 14 ? 19 ns hold time 2 ? 2 ? ns delay time ovf# ? 16 ? 21 ns hold time 2 ? 2 ? ns delay time bgrnt# ? 14 ? 19 ns hold time 2 ? 2 ? ns delay time pbreq# ? 14 ? 19 ns hold time 2 ? 2 ? ns delay time bmreq# ? 16 ? 19 ns hold time 2 ? 2 ? ns delay time rdyout# (internal ready mode) ? 16 ? 21 ns hold time 2 ? 2 ? ns
mb86830 series 41 (continued) (v dd3 = 3.3 v 0.15 v, v ss = 0.0 v, t a = 0 c to + 70 c) (continued) classifica- tion parameter symbol value unit v dd5 = 5.0 v 5% v dd5 = 3.3 v 0.15 v min. max. min. max. output delay time rdyout# * (external ready mode) ? 14 ? 15 ns hold time 2 ? 2 ? ns delay time error# ? 14 ? 21 ns hold time 2 ? 2 ? ns delay time pdown# ? 14 ? 21 ns hold time 2 ? 2 ? ns input setup time ready# 10 ? 10 ? ns hold time 2 ? 2 ? ns setup time mexc# 10 ? 10 ? ns hold time 2 ? 2 ? ns setup time d<31:0> 12 ? 12 ? ns hold time 2 ? 2 ? ns setup time breq# 10 ? 10 ? ns hold time 2 ? 2 ? ns setup time bmack# 10 ? 10 ? ns hold time 2 ? 2 ? ns setup time irl<3:0> asynchronous asynchronous ns hold time asynchronous asynchronous ns setup time wkup# asynchronous asynchronous ns hold time asynchronous asynchronous ns external bus mas- ter input setup time rdwr# 12 ? 12 ? ns hold time 2 ? 2 ? ns setup time as# 12 ? 12 ? ns hold time 2 ? 2 ? ns input setup time asi<3:0> 12 ? 12 ? ns hold time 2 ? 2 ? ns setup time adr<27:2> 12 ? 12 ? ns hold time 2 ? 2 ? ns setup time be2# 12 ? 12 ? ns hold time 2 ? 2 ? ns
mb86830 series 42 (continued) (v dd3 = 3.3 v 0.15 v, v ss = 0.0 v, t a = 0 c to + 70 c) p:period (cycle time) * : rdyout# at the external ready mode is provided for from ready# input. notes ? each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise noted. ? each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v, the input level is 0.4 to 2.4 v, and the input rise time and fall time are 2 ns or less. ? do not leave more than one output pins short-circuited for 1 second or more. ? the external output load capacitance is 30 pf. ? the specifications of pins other than those pins designated as asynchronous inputs and than the rdyout# pin in external ready mode are determined by the rising edge of the external clock (clkin). ? these specifications are subject to change for improvement. ? the reset period requires at least 4 clkin cycles. the pll oscillation stabilization delay time requires at least 4000 clock (clkin) pulses. for 40-mhz (25 ns) clock input, for example, the reset signal must therefore be negated 100 m s later. classifica- tion parameter symbol value unit v dd5 = 5.0 v 5 % v dd5 = 3.3 v 0.15 v min. max. min. max. dramc output delay time ras0# to ras3# ? 12 ? 15 ns hold time 2 ? 2 ? ns delay time cas0# to cas3# ? 12 ? 15 ns hold time 2 ? 2 ? ns delay time dwe0# to dwe3# ? 12 ? 15 ns hold time 2 ? 2 ? ns delay time doe# ? 12 ? 15 ns hold time 2 ? 2 ? ns irc input setup time irq15 to irq8 asynchronous asynchronous ns hold time asynchronous asynchronous ns h level period 2 p + 10 ? 2 p + 10 ? ns l level period 2 p + 10 ? 2 p + 10 ? ns
mb86830 series 43 (4)mb86834-108,-120 (v dd5 = 3.3 v 0.15 v, v dd3 = 2.5 v 0.1 v, v ss = 0.0 v, t a = 0 c to + 70 c) (continued) classifica- tion parameter symbol value unit min. max. clk clkin cycle time ? 25 40 ns clkin high time ? 8 ? ns clkin low time ? 8 ? ns clkin rising time ?? 3ns clkin falling time ?? 3ns output delay time d<31:0> ? 20 ns hold time 2 ? ns delay time adr<27:2> ? 21 ns hold time 2 ? ns delay time be0# to be3# ? 21 ns hold time 2 ? ns delay time asi<3:0> ? 21 ns hold time 2 ? ns delay time cs0# to cs5# ? 21 ns hold time 2 ? ns delay time samepage# ? 21 ns hold time 2 ? ns delay time rdwr# ? 19 ns hold time 2 ? ns delay time lock# ? 19 ns hold time 2 ? ns delay time as# ? 19 ns hold time 2 ? ns delay time ovf# ? 21 ns hold time 2 ? ns delay time bgrnt# ? 19 ns hold time 2 ? ns delay time pbreq# ? 19 ns hold time 2 ? ns delay time bmreq# ? 19 ns hold time 2 ? ns
mb86830 series 44 (continued) (v dd5 = 3.3 v 0.15 v, v dd3 = 2.5 v 0.1 v, v ss = 0.0 v, t a = 0 c to + 70 c) (continued) classifica- tion parameter symbol value unit min. max. output delay time rdyout# (internal ready mode) ? 21 ns hold time 2 ? ns delay time rdyout# * (external ready mode) ? 15 ns hold time 2 ? ns delay time error# ? 21 ns hold time 2 ? ns delay time pdown# ? 21 ns hold time 2 ? ns input setup time ready# 10 ? ns hold time 2 ? ns setup time mexc# 10 ? ns hold time 2 ? ns setup time d<31:0> 12 ? ns hold time 2 ? ns setup time breq# 10 ? ns hold time 2 ? ns setup time bmack# 10 ? ns hold time 2 ? ns setup time irl<3:0> asynchronous ns hold time asynchronous ns setup time wkup# asynchronous ns hold time asynchronous ns external bus mas- ter input setup time rdwr# 12 ? ns hold time 2 ? ns setup time as# 12 ? ns hold time 2 ? ns input setup time asi<3:0> 12 ? ns hold time 2 ? ns setup time adr<27:2> 12 ? ns hold time 2 ? ns setup time be2# 12 ? ns hold time 2 ? ns
mb86830 series 45 (continued) (v dd5 = 3.3 v 0.15 v, v dd3 = 2.5 v 0.1 v, v ss = 0.0 v, t a = 0 c to + 70 c) p:period (cycle time) * : rdyout# at the external ready mode is provided for from ready# input. notes ? each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise noted. ? each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v, the input level is 0.4 to 2.4 v, and the input rise time and fall time are 2 ns or less. ? do not leave more than one output pins short-circuited for 1 second or more. ? the external output load capacitance is 30 pf. ? the specifications of pins other than those pins designated as asynchronous inputs and than the rdyout# pin in external ready mode are determined by the rising edge of the external clock (clkin). ? these specifications are subject to change for improvement. ? the reset period requires at least 4 clkin cycles. the pll oscillation stabilization delay time requires at least 4000 clock (clkin) pulses. for 40 mhz (25 ns) clock input, for example, the reset signal must therefore be negated 100 m s later. classifica- tion parameter symbol value unit min. max. dram- coutput delay time ras0# to ras3# ? 15 ns hold time 2 ? ns delay time cas0# to cas3# ? 15 ns hold time 2 ? ns delay time dwe0# to dwe3# ? 15 ns hold time 2 ? ns delay time doe# ? 15 ns hold time 2 ? ns irc input setup time irq15 to irq8 asynchronous ns hold time asynchronous ns h level period 2 p + 10 ? ns l level period 2 p + 10 ? ns
mb86830 series 46 (5)MB86835 (v dd5 = v dd3 = 3.3 v 0.15 v, v ss = 0.0 v, t a = 0 c to + 70 c) (continued) classifica- tion parameter symbol value unit MB86835 min. max. clk clkin cycle time ? 25 100 ns clkin high time ? 8 ? ns clkin low time ? 8 ? ns clkin rising time ?? 3ns clkin falling time ?? 3ns output delay time d<31:0> ? 20 ns hold time 2 ? ns delay time adr<27:2> ? 21 ns hold time 2 ? ns delay time be0# to be3# ? 21 ns hold time 2 ? ns delay time asi<3:0> ? 21 ns hold time 2 ? ns delay time cs0# to cs5# ? 21 ns hold time 2 ? ns delay time samepage# ? 21 ns hold time 2 ? ns delay time rdwr# ? 19 ns hold time 2 ? ns delay time lock# ? 19 ns hold time 2 ? ns delay time as# ? 19 ns hold time 2 ? ns delay time ovf# ? 21 ns hold time 2 ? ns delay time bgrnt# ? 19 ns hold time 2 ? ns delay time pbreq# ? 19 ns hold time 2 ? ns delay time bmreq# ? 19 ns hold time 2 ? ns
mb86830 series 47 (continued) (v dd3 = 3.3 v 0.15 v, v ss = 0.0 v, t a = 0 c to + 70 c) (continued) classifica- tion parameter symbol value unit MB86835 min. max. output delay time rdyout# (internal ready mode) ? 21 ns hold time 2 ? ns delay time rdyout# * (external ready mode) ? 15 ns hold time 2 ? ns delay time error# ? 21 ns hold time 2 ? ns delay time pdown# ? 21 ns hold time 2 ? ns input setup time ready# 10 ? ns hold time 2 ? ns setup time mexc# 10 ? ns hold time 2 ? ns setup time d<31:0> 12 ? ns hold time 2 ? ns setup time breq# 10 ? ns hold time 2 ? ns setup time bmack# 10 ? ns hold time 2 ? ns setup time irl<3:0> asynchronous ns hold time asynchronous ns setup time wkup# asynchronous ns hold time asynchronous ns external bus mas- ter input setup time rdwr# 12 ? ns hold time 2 ? ns setup time as# 12 ? ns hold time 2 ? ns input setup time asi<3:0> 12 ? ns hold time 2 ? ns setup time adr<27:2> 12 ? ns hold time 2 ? ns setup time be2# 12 ? ns hold time 2 ? ns
mb86830 series 48 (continued) (v dd3 = 3.3 v 0.15 v, v ss = 0.0 v, t a = 0 c to + 70 c) p:period (cycle time) * : rdyout# at the external ready mode is provided for from ready# input. notes ? each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise noted. ? each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v, the input level is 0.4 to 2.4 v, and the input rise time and fall time are 2 ns or less. ? do not leave more than one output pins short-circuited for 1 second or more. ? the external output load capacitance is 30 pf. ? the specifications of pins other than those pins designated as asynchronous inputs and than the rdyout# pin in external ready mode are determined by the rising edge of the external clock (clkin). ? these specifications are subject to change for improvement. ? the reset period requires at least 4 clkin cycles. the pll oscillation stabilization delay time requires at least 4000 clock (clkin) pulses. for 40 mhz (25 ns) clock input, for example, the reset signal must therefore be negated 100 m s later. ? an ac characteristic of pins and internal maximum operation frequency is separately defined. ? the maximum operation frequency of an external bus is 40mhz though the maximum internal operation frequency are 80 mhz or 100 mhz (clkin min.=25ns).therefore,when an external bus is used with 40mhz, an internal frequency are 84 mhz and 100 mhz. ? relation between external bus clock and internal clock classifica- tion parameter symbol value unit MB86835 min. max. dramc output delay time ras0# to ras3# ? 15 ns hold time 2 ? ns delay time cas0# to cas3# ? 15 ns hold time 2 ? ns delay time dwe0# to dwe3# ? 15 ns hold time 2 ? ns delay time doe# ? 15 ns hold time 2 ? ns irc nput setup time irq15 to irq8 asynchronous ns hold time asynchronous ns h level period 2 p + 10 ? ns l level period 2 p + 10 ? ns clkin MB86835(84mhz) 1 2 3 4 5 20 mhz 20 mhz 40 mhz 60 mhz 80 mhz n/a 33.3 mhz 33.3 mhz 66.6 mhz n/a n/a n/a 40 mhz 40 mhz 80 mhz n/a n/a n/a
mb86830 series 49 (6)mb86836-90,-108(preliminary) (v dd5 = 3.3 v 0.15 v, v dd3 = 2.5 v 0.1 v, v ss = 0.0 v, t a = 0 c to + 70 c) (continued) classifica- tion parameter symbol value unit min. max. clk clkin cycle time ? 25 40 ns clkin high time ? 8 ? ns clkin low time ? 8 ? ns clkin rising time ?? 3ns clkin falling time ?? 3ns output delay time d<31:0> ? 20 ns hold time 2 ? ns delay time adr<27:2> ? 21 ns hold time 2 ? ns delay time be0# to be3# ? 21 ns hold time 2 ? ns delay time asi<3:0> ? 21 ns hold time 2 ? ns delay time cs0# to cs5# ? 21 ns hold time 2 ? ns delay time samepage# ? 21 ns hold time 2 ? ns delay time rdwr# ? 19 ns hold time 2 ? ns delay time lock# ? 19 ns hold time 2 ? ns delay time as# ? 19 ns hold time 2 ? ns delay time ovf# ? 21 ns hold time 2 ? ns delay time bgrnt# ? 19 ns hold time 2 ? ns delay time pbreq# ? 19 ns hold time 2 ? ns delay time bmreq# ? 19 ns hold time 2 ? ns
mb86830 series 50 (continued) (v dd5 = 3.3 v 0.15 v, v dd3 = 2.5 v 0.1 v, v ss = 0.0 v, t a = 0 c to + 70 c) (continued) classifica- tion parameter symbol value unit min. max. output delay time rdyout# (internal ready mode) ? 21 ns hold time 2 ? ns delay time rdyout# * (external ready mode) ? 15 ns hold time 2 ? ns delay time error# ? 21 ns hold time 2 ? ns delay time pdown# ? 21 ns hold time 2 ? ns input setup time ready# 10 ? ns hold time 2 ? ns setup time mexc# 10 ? ns hold time 2 ? ns setup time d<31:0> 12 ? ns hold time 2 ? ns setup time breq# 10 ? ns hold time 2 ? ns setup time bmack# 10 ? ns hold time 2 ? ns setup time irl<3:0> asynchronous ns hold time asynchronous ns setup time wkup# asynchronous ns hold time asynchronous ns external bus mas- ter input setup time rdwr# 12 ? ns hold time 2 ? ns setup time as# 12 ? ns hold time 2 ? ns input setup time asi<3:0> 12 ? ns hold time 2 ? ns setup time adr<27:2> 12 ? ns hold time 2 ? ns setup time be2# 12 ? ns hold time 2 ? ns
mb86830 series 51 (continued) (v dd5 = 3.3 v 0.15 v, v dd3 = 2.5 v 0.1 v, v ss = 0.0 v, t a = 0 c to + 70 c) p:period (cycle time) * : rdyout# at the external ready mode is provided for from ready# input. notes ? each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise noted. ? each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v, the input level is 0.4 to 2.4 v, and the input rise time and fall time are 2 ns or less. ? do not leave more than one output pins short-circuited for 1 second or more. ? the external output load capacitance is 30 pf. ? the specifications of pins other than those pins designated as asynchronous inputs and than the rdyout# pin in external ready mode are determined by the rising edge of the external clock (clkin). ? these specifications are subject to change for improvement. ? the reset period requires at least 4 clkin cycles. the pll oscillation stabilization delay time requires at least 4000 clock (clkin) pulses. for 40 mhz (25 ns) clock input, for example, the reset signal must therefore be negated 100 m s later. ? an ac characteristic of pins and internal maximum operation frequency is separately defined. ? the maximum operation frequency of an external bus is 40mhz though the maximum internal operation frequency are 90 mhz or 100 mhz (clkin min.=25ns).therefore,when an external bus is used with 40mhz, an internal frequency is 80 mhz ? relation between external bus clock and internal clock *: mb86836 108mhz version is under developement. classifica- tion parameter symbol value unit min. max. dram- coutput delay time ras0# to ras3# ? 15 ns hold time 2 ? ns delay time cas0# to cas3# ? 15 ns hold time 2 ? ns delay time dwe0# to dwe3# ? 15 ns hold time 2 ? ns delay time doe# ? 15 ns hold time 2 ? ns irc input setup time irq15 to irq8 asynchronous ns hold time asynchronous ns h level period 2 p + 10 ? ns l level period 2 p + 10 ? ns clkin mb86836(90mhz) mb86836(108mhz)* 1 2 3 4 5 1 2 3 4 5 27 mhz 27 mhz 54 mhz 81 mhz n/a n/a 27 mhz 54 mhz 81 mhz 108 mhz n/a 33.3 mhz 33.3 mhz 66.6 mhz n/a n/a n/a 33.3 mhz 66.6 mhz 100mhz n/a n/a 36 mhz 36mhz 72 mhz n/a n/a n/a 36mhz 72 mhz 108mhz n/a n/a 40 mhz 40 mhz 80 mhz n/a n/a n/a 40 mhz 80 mhz n/a n/a n/a
mb86830 series 52 n timing diagram ? reset timing ? input/output timing 1 clkin note : clkin is steady, and raise reset input "h", please after at least 100msec. reset# longer than four clock cycle clkin input pins outpou pins input/output pins input pins : breq#, bmack# outpou pins : be0# to be1#, be3#, cs0# to cs5#, samepage#, lock#, ovf#, bgrnt#, pbreq#, bmreq#, error#, pdown#, ras0# to ras3#, cas0# to cas3#, dwe0# to dwe3#, doe# input/output pins : d<31: 0>, asi<3: 0>, rdwr#, be2# setup setup hold hold hold valid delay valid delay hold input data output data
mb86830 series 53 ? input/output timing 2 ? input/output timing 3 ? input/output timing 4 clkin input pins output pins input/output pins imput pins : ready#, mexc# output pins : rdyout# (internal ready mode) input/output pins : adr<27: 2> setup setup hold valid delay hold hold hold valid delay input data output data clkin as# setup hold hold valid delay input data output data ready # rdyout # (external ready mode) valid delay hold
mb86830 series 54 n architecture the mb86830 series is a line of 32-bit risc processors running at an operating frequency of 100 mhz, providing high performance of 121 vax-mips. as products belong to the fujitsu sparclite family, the mb86830 series is based on the sparc architecture and are thus upward code-compatible with the conventional products in the sparclite family. the mb86830 series was developed in particular for embedded applications, providing high per- formance and high level of integration when used as embedded controllers. the mb86830 series has an efficient set of instructions and is hardwired so that most of them can be executed in one cycle. the iu (integer unit) features five pipelined execution stages designed for processing data interlocks, providing a branch handler optimized for for efficient transition of control and a bus interface for processing one- cycle bus access for on-chip memory. the internal register file consisting of a stack of eight windows, made up of 136 registers in total, speeds up inter- rupt response and context switching. the register file minimizes memory access during procedure linkage and facilitates parameter passing and variable assignment. the mb86830 series contains instruction and data caches to isolate processor operation from external memory. these caches are designed for highest flexibility so that it can lock each entry to improve the performance of the entire system. the independent instruction and internal data buses serve as high-bandwidth interfaces between the iu (integer unit) and the on-chip caches. these buses support single-cycle instruction execution and single-cycle data trans- fer between the iu and caches in parallel. the mb86830 series incorporates an integer multiplier and auxiliary hardware for division. the mb86830 series can therefore execute 32-bit integer multiplication in five cycles, 16-bit integer multiplication in three cycles, 8-bit integer multiplication in two cycles, and integer multiplication by 0 in one cycle. 1. main features (1)high-speed execution of instructions most of the instructions in most programs are simple, designing the programs so as to execute such simple instruc- tions as fast as possible dramatically improves the program execution time. (2)high-capacity register set the register set reduces the number of required accesses to data memory. registers are organized into a stack of groups called register windows, allowing themselves to be used efficiently for high-priority tasks such as interrupt services and operating system working registers. a stack of (overlapping) register windows also contributes to sim- plifying parameter passing during procedure linkage, thereby reducing the code size of most programs. (3)on-chip caches the mb86830 series incorporates data and instruction caches so that the processor can work independently of the slower memory subsystem. these caches are implemented in two-way set-associative configuration on the mb86831/832; they are directly mapped on the mb86833. (4)locking entries in caches the mb86830 series can lock both of data and instruction entries in their respective caches, ensuring high perfor- mance in processing important or frequently called routines. each cache offers maximum flexibility so that entries can be locked in all or selective part of the cache. (5)bus interface the mb86830 series supports programmable chip selection, a wait state generator, and fast page mode dram, minimizing the necessity of connecting external circuits. (6)on-chip dram controller the on-chip dram controller supports fast page mode and edo drams. it also controls self-refreshing of dram in sleep mode (low power consumption mode).
mb86830 series 55 (7)on-chip interrupt controller the on-chip interrupt controller accepts interrupt inputs through eight channels, allowing a trigger mode to be set independently for each of the channels. the interrupt request accepted according to the trigger mode is encoded and output to the processor. (8)multiplier circuit the mb86830 series incorporates a multiplier circuit which can be selectively set to an operating clock frequency of x1, x2, x3, x4,or x5 of the external clock frequency, allowing the processor to run at high speed. (9) instruction set the mb86830 series supports high-speed integer multiply instructions which are executed in five, three, and two cycles respectively for 32-, 16-, and 8-bit multiplications. the integer divide step instruction is near 10 times faster in divide time than the previous sparc implementation. the scan instruction supports the function for detecting 1 or 0 at the msb in a word in a single cycle. 2. cpu the cpu core of the mb86830 series is a high-performance version implemented by full custom design of the sparc architecture. the cpu core contains a compact circuitry for integrating peripheral circuits, designed to be customizable to a variety of applications. the cpu core consists of three function units: instruction, address, and execution blocks (see integer operation unit internal block diagram). the role of five execution stages for instruction pipelining is to decode all instructions and generate control signals for other blocks. the five pipelined stages are the fetch (f), decode (d), execute (e), memory (m), and write back (w) stages. the instruction memory returns an instruction addressed at stage (f), the register file returns an op- erand addressed at stage (d), the alu perform calculation to obtain the result at stage(e), the external memory is addressed at stage(m), and the register file is written back at stage (w).
mb86830 series 56 ? integer operation unit internal block diagram 3. address space the mb86830 series has a wide addressable range in which user and supervisor spaces can be defined indepen- dently. of 30 lines of addresses, eight lines of address space identifiers (asi) are used to distinguish between protected and unprotected spaces. tow of 256 different asi values are used to define the user data and user in- struction spaces; the rest are used to define the supervisor space. when a reset, synchronous trap, or asynchronous trap occurs, the processor enters the supervisor mode. in the supervisor mode, the processor executes instructions in the supervisor space and transfers data. the processor can access other asi values even when staying in the supervisor mode. the processor can use the remaining asi values, excluding the reserved values, to allocate other spaces as application definable spaces. by distinguishing between the user and supervisor spaces, hardware can prevent inadvertent or unauthorized ac- cess to system resources. when a real-time operating system (rtos) is developed, for example, individual spac- es provide the mechanism for separating the rtos space efficiently from the user space. 4. registers the register set of the mb86830 series is made up of the registers to be used for general-purpose functions and those to be used for control and status report purpose. the mb86830 series has 136 general-purpose registers divided into eight global registers and a stack of eight register blocks (register windows). each register window incorporates 24 registers, of which eight registers are local to that window, eight out registers are overlapping the next register window, and eight in registers are overlapping the previous register window. (see general register composition.) this register configuration allows a parameter to be passed to a subroutine. the next register window is made ir e_ir m_ir w_ir instruction block (i block) i data adder read1 read2 read3 write register file ab inc (+4) 0 tbr pc d_pc e_pc m_pc alu / shifter r psr/wim/y data address w st_align id_align address block (a block) execution block (e block) d address d data i address
mb86830 series 57 available b writing the parameter to be passed to the out register and using a procedure call to decrement the window pointer by one. the passed parameter remains in the in registers in the current register window and can be used by that subroutine. register windows improve the performance of embedded applications. this is because these windows serve as the local variable caches for storing interrupt, subroutine, context, or operating system variables without increasing overhead. in addition, the code size of programs can be reduced by using an efficient method of executing proce- dure linkage without optimizing the code using an inlining compiler. the register file consists of 4-port registers: 3-port read and 1-port write registers. even the store instruction can therefore be executed in one cycle, which requires three operands to be read from the register file. the control and status registers are divided into those defined in the sparc architecture and those mapped into the alternate address space for controlling the functions of peripheral devices. ? general register composition w7 ins locals outs cwp outs ins locals outs ins locals ins outs locals outs ins locals outs ins locals outs ins locals outs ins locals w1 w5 w3 wim w0 w6 w4 w2 restore save
mb86830 series 58 5. instruction set the mb86830 series is upward code-compatible with other sparc processors. the mb86830 series now sup- ports additional instructions to improve performance, which were previously not directly supported. in addition to a set of already supported sparc instructions, the mb86830 series has been provided with the integer multiply and integer divide step instructions as well as the scan instruction for detecting 1 or 0 at the msb. for the list of supported instructions, see the instruction set below. ? instruction set 6. interrupts one of the key criteria to determine whether a processor is suitable for embedded applications is whether the pro- cessor can completely service interrupts within the minimum interrupt processing time. the processors implement- ed as the mb86830 series guarantee not only short average wait time but also short maximum wait time. the interrupt response time is the sum of the time for the processor to complete the current task after recognizing an interrupt and the time for the processor to start executing the interrupt service routine. the mb86830 series offers a variety of functions to minimize the both factors. to minimize the time to complete the current task, the mb86830 series is designed so that the task can be inter- rupted easily or it can be completed in a minimum of cycles. for this purpose, the mb86830 series implements the cache system that updates only one word at a time using a prefetch buffer when a cache miss occurs, inter- ruptible integer division using a divide step instruction, high-speed multiplication using a multiplier, and a 4-word write buffer for processing a pending bus transaction. to minimize the time required for starting executing the interrupt service routine, the processor switches the reg- ister window to a new one upon detection of an interrupt. this function allows the service routine to be executed logical arithmetic/shift data movement condition codes unchanged and or xor and not or not xnor condition codes set and or xor and not or not xnor condition codes unchanged add subtract multiply (signed/unsigned) scan sethi shift left logical shift right logical shift right arithmetic condition codes set add subtract multiply (signed/unsigned) multiply step divide step extended and condition codes unchanged add subtract extended and condition codes set add subtract tagged and condition codes set (with and without trap on overflow) add subtract to user/supervisor space signed load byte load half-word load word load double word store byte store half-word store word store double word to user space unsigned load byte load half-word to alternate space signed load byte load half-word load word load double word store byte store half-word store word store double word to alternate space unsigned load byte load half-word atomic operation in user space swap word load/store unsigned byte atomic operation in alternate space swap word load/store unsigend byte control transfer conditional branch conditional trap call return save restore jump and link read/write control register read psr read wim rdasr write psr write wim wrasr read tbr read y write tbr write y
mb86830 series 59 without saving the current register in advance. the user can also lock the service routine in the cache, allowing faster processing with the routine. at this time, the on-chip data cache can be used as a high-speed local stack to minimize the delay in accessing the routine variable in the service routine. the mb86830 series has a maximum of 15 interrupt levels to directly support 15 interrupt sources. the highest interrupt level is nonmaskable. 7. caches the mb86830 series incorporates independent data and instruction caches, allowing a high-performance system to be constructed without the need for high-speed external memory or relevant control logics. the caches are mapped onto physical addresses. the instruction cache consists of: 64 units/2 banks on the mb86831/835, 128 units/2 banks on the mb86832/836, 256 units/2 banks on a 32-byte line on the mb86834, and 64 units/1 bank on a 16-byte line on the mb86833. the data cache consists of: 64 units/2 banks on the mb86831/835, 64 units/1 bank on a 16-byte line on the mb86833, 128 units/2 banks on the mb86832/836, and 256 units/2 banks on a 32-byte line on the mb86834. (see the com- position of the data cache and the composition of the instruction cash.) each line is divided into 4-byte sub- blocks. when a cache miss occurs, the cache is updated in one word (4 bytes) or four words (16 bytes), selectively. updating the cache in one word eliminates the wait time for an interrupt generated for replacing a long cache line; updating the cache in four words can result improvement in cache hit rate. updating the cache in four words uses the burst mode. the instruction prefetch buffer fetches the next instruction in advance, assuming that it corresponds to the next instruction cache miss. the caches can be used in the normal mode or in either of two lock modes. in the normal mode, the cache in two- way set-associative configuration replaces one of two corresponding entries using the lru (least recently used) algorithm. as an alternate method, the entire cache or only the selected entry can be locked depending on the lock mode in use. the lock mode can lock a time-critical routine in the cache. the global cache lock mode locks the entries in the entire instruction or data cache. the two control bits in the cache control register enable or disable the lock in the instruction and data caches. once an entire cache is locked, any valid entry in the cache cannot be replaced. to ensure optimum performance, how- ever, an invalid entry is updated when it is accessed. this update is performed automatically without generating time penalty.the instruction or data entry selected by local cache locking can be locked automatically in the corre- sponding cache. this mechanism can ensure the fastest response from a certain important interrupt routine by locking the code of the routine in the cache. also, of those routines which can be removed from the cache, frequently used ones should be given priority in per- formance in some cases. in such cases, the entries can be locked. the local cache lock mode can lock individual entries or lock entries automatically by hardware. to lock each entry, the lock bit in the corresponding cache tag line is set by software. for automatic cache locking, the lock function is enabled or disabled depending on the bit in the corresponding cache control register. the enable/disable bit is set at the beginning of the routine for which the entry is to be locked. the location of cache access generated with the bit enabling the lock function is locked in the cache. automatic cache locking does not involve overhead other than the initial setting cycle. when a cache entry is unlocked, the data cache assign the cache entry only at load time based on the write- through update policy. the write operation is buffered and the processor can continue execution while data is be- ing written back to memory. in contrast, the data written to the locked data cache location is not written to main memory. the above method reduces external bus access and allows part of the data cache to be used as on-chip ram which is not mapped into external memory. the data and instruction caches are designed to be accessed through the independent data and instruction buses to load/write data from/to the cache at a maximum speed of 1 cpi (clock/instruction).
mb86830 series 60 ? the composition of the data cache (for mb86832). ? the composition of the instruction cash (for mb86832). 8. bus interface the bus interface unit (biu) is designed to simplify the interface between the mb86830 series and other parts of the system. the non-multiplexed address bus and data bus allow a high-speed system to be constructed easily. also, the internal circuitry allows such a system to be constructed with a minimum of external hardware. the bus interface supports programmable wait state generation, chip select output by address decoding, same- page detection for supporting page mode dram, booting from 8/16/32-bit memory, and a automatic reload timer for refreshing dram. in addition, the burst mode can be used to perform cache line fill operation at high speed. 9. dram controller with the dram controller controlling dram, the mb86830 series can write/read data to/from dram. the dram controller can control up to four banks on the mb86831/832/834 or only one bank on the mb86833/835. the fast page mode, dram mode, or edo dram mode can be selected depending on the register setting. the dram set 2 set 1 31 12 8 entry 0 address tag lock, valid, lru . . sub-block . . (tag) (entry) 0 127 address tag set 2 set 1 31 12 0 8 entry address tag lock, valid, lru . . sub-block . . (tag) (entry) 0 127 address tag
mb86830 series 61 controller also controls the ras and cas to place dram in the self-refresh mode when the processor enters the sleep mode (low power consumption mode). the mb86836 has no dram controller. 10. interrupt controller (irc) the interrupt controller (irc) accepts interrupts inputs through eight channels, depending on the trigger mode and mask bit set for each of the channels. when accepting an interrupt, the interrupt controller encodes it according to the interrupt priority level and outputs the interrupt level to the processor. the interrupt level remains held unless it is cleared by the processor. the processor is not therefore informed of the next interrupt. 11. multiplier circuit the clksel0, clksel1, and clksel2 pins can be used to select the multiplier circuit to be used. the 1, 2, 3, 4, or 5 multiplier circuits are supported, which allow the processor to run faster. 12. iu (integer unit) dedicated registers (not memory mapped) (1)processor status register (psr) bit 23 to bit 20 :integer condition code [icc] (n:negative = 1, z:zero = 1, v:overflow = 1, c:carry = 1) bit 19 to bit 12 :reserved[0write, dont care for read] bit 11 to bit 8 :processor interrupt level [pil] (value = 1 to 15, rst = x) bit 7 :supervisor mode [s] (supervisor = 1, user = 0, rst = 1) bit 6 :prior s mode [ps] bit 5 :enable trap [et] (enable = 1, disable = 0, rst = 0) bit 4 to bit 3 :reserved [0write, dont care for read] bit 2 to bit 0 :current window point [cwp] (value = 0 to 7, rst = x) x:dont care (2)window invalid mask register (wim) bit 31 to bit 8 :reserved [0write, dont care for read] bit 7 to bit 0 :window mask [w7 to w0] (invalid = 1, valid = 0, rst = x) x:dont care (3)trap base register (tbr) bit 31 to bit 12 :trap base address [tba] (rst = x) bit 11 to bit 4 :trap type [tt] (rst = x) x:dont care bit ? 31 28 27 24 23 20 19 12 11 8 7 6 5 4 3 2 0 0 0 0 0 h 1 1 1 1 h icc reserved pil s ps et reserved cwp nz vc bit ? 31 876543210 reserved w7 w6 w5 w4 w3 w2 w1 w0 bit ? 31 12 11 4 3 0 tba tt 0 0 0 0
mb86830 series 62 (4)y register (y) (5)ancillary state register 17 (asr17) bit 31 to bit 1 :reserved [0write, dont care for read] bit 0 :single vector trapping [svt] (enable = 1, disable = 0, rst = 0) 13. iu (integer unit) general-purpose registers (not memory mapped) the iu (integer unit) contains 136 32-bit general-purpose registers for holding arguments for operations and their results. of these registers, only 32 registers can be accessed through blocks called register windows. the integer unit has eight register windows. the register window to be used is determined by the cwp bits (bits 2 to 0) in the processor status register (psr). each register window consists of eight global registers available commonly to all register windows and 24 registers (in-register 8, local register 8, out-register 8). the in-reg- isters and out-registers are used commonly between adjacent register windows. (1)zero register (r0) bit 31 to bit 0 :0 (2)general register (r1 to r31) dont care at reset. 14. bit map of register with built-in cpu core (1)cache/biu control register (cbir) asi= 0x01, address= 0x00000000 h bit 31 to bit 10 :reserved [0write, dont care for read] bit 9 to bit 8 :non-cacheable wait-state [dont care for read] bit 7 :cacheability enable [dont care for read] (enable = 1, disable = 0, rst = 0) bit 6 :reserved [0write, dont care for read] bit 5 :write buffer enable (enable = 1, disable = 0, rst = 0) bit 4 :prefetch buffer enable (enable = 1, disable = 0, rst = 0) bit 3 :data cache lock (lock = 1, unlock = 0, rst = 0) bit 2 :data cache enable (enable = 1, disable = 0, rst = 0) bit 1 :instruction cache lock (lock = 1, unlock = 0, rst = 0) bit 0 :instruction cache enable (enable = 1, disable = 0, rst = 0) bit ? 31 0 bit ? 31 10 reserved svt bit ? 31 0 0 bit ? 31 0 bit ? 31 10 98 76543210 reserved
mb86830 series 63 (2)lock control register (lcr) asi= 0x01, address= 0x00000004 h bit 31 to bit 2 :reserved [0write, dont care for read] bit 1 :data cache entry auto lock (enable = 1, disable = 0, rst = 0) bit 0 :instruction cache entry auto lock (enable = 1, disable = 0, rst = 0) (3)lock control save register (lcsr) asi = 0x01, address = 0x00000008 h bit 31 to bit 2 :reserved [0write, dont care for read] bit 1 :previous data cache auto lock (off = 0, on = 1, rst = 0) bit 0 :previous instruction cache auto lock (off = 0, on = 1, rst = 0) (4)restore lock control register (rlcr) asi = 0x01, address = 0x00000010 h bit 31 to bit 1 :reserved [0write, dont care for read] bit 0 :restore lock control register (restore = 1, ignore = 0, rst = 0) (5)bus control register (bcr) asi = 0x01, address = 0x00000020 h bit 31 to bit 2 :reserved [0write, dont care for read] bit 1 :data burst enable (enable = 1, disable = 0, rst = 0) bit 0 :instruction burst enable (enable = 1, disable = 0, rst = 0) (6)system support control register (sscr) asi = 0x01, address = 0x00000080 h bit 31 to bit 8 :reserved [0write, dont care for read] bit 7 :dram burst enable (enable = 1, disable = 0, rst = 0) bit 6 :dram controller enable (enable = 1, disable = 0, rst = 0) bit 5 :same page enable (enable = 1, disable = 0, rst = 0) bit 4 :cs enable (enable = 1, disable = 0, rst = 0) * bit 3 :programmable wait-state (enable = 1, disable = 0, rst = 1) bit 2 :timer on/off (enable = 1, disable = 0, rst = 0) bit 1 to bit 0 :reserved 0write, dont care for read] *:cs0 is always enable. bit ? 31 210 reserved bit ? 31 210 reserved bit ? 31 10 reserved bit ? 31 210 reserved bit ? 31 876543210 reserved
mb86830 series 64 (7)same page mask register (spgmr) asi = 0x01, address = 0x00000120 h bit 31 :reserved [0write, dont care for read] bit 30 to bit 23 :asi<7:0>mask (care = 0, dont care = 1, rst = x) bit 22 to bit 1 :address<31:10>mask (care = 0, dont care = 1, rst = x) bit 0 :reserved [0write,dont care for read] x:dont care (8)address range specifier register (arsr) asi = 0x01, address = 0x00000124 h to 0x00000134 h bit 31 :reserved [0write, dont care for read] bit 30 to bit 23 :asi<7:0>(rst = x) * bit 22 to bit 1 :address<31:10>(rst = x) * bit 0 :reserved [0write, dont care for read] *cs0 is fixed to address<31: 15>=0,address<14: 10>=0,asi<7:0>=0x09. x:dont care (9)address mask register (amr) asi = 0x01, address = 0x00000140 h to 0x00000154 h bit 31 :reserved [0write, dont care for read] bit 30 to bit 23 :asi<7:0>mask (cs0:rst = 0, cs1 to cs5:rst = x) bit 22 to bit 1 :address<31:10>mask (cs0:rst = <31:15> = 0, <14:10> = 0x1f, cs1 to cs5:rst = x) bit 0 :reserved [0write, dont care for read] x:dont care (10)wait state specifier register (wssr) asi = 0x01, address = 0x00000160 h to 0x00000168 h bit 31 to bit 27,bit 18 to bit 14 :count 1 (cs0:rst = 0x1f, cs1 to cs5:rst = 0) bit 26 to bit 22,bit 13 to bit 9 :count 2 (cs0:rst = 0x1f, cs1 to cs5:rst = 0) bit 21,bit 8 :wait enable (on = 1, off = 0,cs0:rst = 1, cs1 to cs5:rst = 0) bit 20,bit 7 :single cycle non burst mode (on = 1, off = 0,rst = 0) bit 19,bit 6 :override (on = 1, off = 0, cs0 = 1, cs1 to cs5 = 0) bit 5,bit 4 :single cycle burst mode (on = 1, off = 0, rst = 0) bit 3 to bit 0 :reserved [0write, dont care for read] bit ? 31 30 23 22 1 0 asi<7:0>mask address<31:10>mask bit ? 31 30 23 22 1 0 asi<7:0> address<31:10> bit ? 31 30 23 22 1 0 asi<7:0>mask address<31:10>mask bit ? 31 27 26 22 21 20 19 18 14 13 9 8 7 6 5 4 3 0 count 1 count 2 count 1 count 2
mb86830 series 65 (11)bus width/cacheable register (bwcr) asi = 0x01, address = 0x0000016c h bit 31 to bit 24 :reserved [0write, dont care for read] bit 23,bit 21,bit 19,bit 17,bit 15,bit 13 :internal/external cacheable (0 = external, 1 = internal) bit 22,bit 20,bit 18,bit 16,bit 14,bit 12 :cacheable (0 = cacheable, 1 = noncacheable) bit 11 to bit 10,bit 9 to bit 8,bit 7 to bit 6,bit 5 to bit 4, bit 3 to bit 2 :bus width control bit bit 1 to bit 0 :reserved [0write, dont care for read] (12)dram refresh timer register (reftmr) asi = 0x01, address = 0x00000174 h bit 31 :test mode [0write, dont care for read] bit 30 to bit 16 :reserved [0write, dont care for read] bit 15 to bit 0 :timer value (rst = 0xffff) (13)dram refresh timer pre-load (drld) asi = 0x01, address = 0x00000178 h bit 31 :3 cycle mode (on = 1, off = 0, rst = 0) bit 30 to bit 16 :reserved [0write, dont care for read] bit 15 to bit 0 :timer pre-load value (rst = 0xffff) (14)ancillary version register (ver2)[read only] asi = 0x01, address = 0x00020000 h bit 31 to bit 16 :reserved [dont care for read] bit 15 to bit 0 :version (mb86831:value = 0, mb86832:value = 1, mb86833:value = 2, mb86834:value = 3, MB86835:value = 4, mb86836:value = 1) (15)sleep mode register (slpmd)[write only] asi = 0x01, address = 0x00020004 h bit 31 to bit 1 :reserved bit 0 :sleep mode (on = 1, off = 0, rst = 0) bit ? 31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved cs5 cs4 cs3 cs2 cs1 cs0 cs5 cs4 cs3 cs2 cs1 bit ? 31 30 16 15 0 reserved timer value bit ? 31 30 16 15 0 reserved timer pre-load value bit ? 31 16 15 0 reserved version bit ? 31 10 reserved
mb86830 series 66 15. bit map of register for cash access (1)instruction tag lock bit (iclock) [wite only] asi = 0x02 capacity 16 kb bank 1:address = 0x00000000 h to 0x00001fe0 h (+32) bank 2:address = 0x80000000 h to 0x80001fe0 h (+32) capacity 8 kb bank 1:address = 0x00000000 h to 0x00000fe0 h (+32) bank 2:address = 0x80000000 h to 0x80000fe0 h (+32) capacity 4 kb bank 1:address = 0x00000000 h to 0x000007e0 h (+32) bank 2:address = 0x80000000 h to 0x800007e0 h (+32) capacity 2 kb bank 1:address = 0x00000000 h to 0x000003f0 h (+16) bank 2:address = 0x80000000 h to 0x800003f0 h (+16) capacity 1 kb bank 2:address = 0x80000000 h to 0x800003f0 h (+16) bit 31 to bit 1 :reserved [0write, dont care for read] bit 0 :entry lock (lock = 1, unlock = 0, rst = 0) (2)data tag lock bit (dclock)[wite only] asi = 0x03 capacity 16 kb bank 1:address = 0x00000000 h to 0x00001fe0 h (+32) bank 2:address = 0x80000000 h to 0x80001fe0 h (+32) capacity 8 kb bank 1:address = 0x00000000 h to 0x00000fe0 h (+32) bank 2:address = 0x80000000 h to 0x80000fe0 h (+32) capacity 4 kb bank 1:address = 0x00000000 h to 0x000007e0 h (+32) bank 2:address = 0x80000000 h to 0x800007e0 h (+32) capacity 2 kb bank 1:address = 0x00000000 h to 0x000003f0 h (+16) bank 2:address = 0x80000000 h to 0x800003f0 h (+16) capacity 1 kb bank 2:address = 0x80000000 h to 0x800003f0 h (+16) bit 31 to bit 1 :reserved [0write, dont care for read] bit 0 :entry lock (lock = 1, unlock = 0, rst = 0) bit ? 31 10 reserved bit ? 31 10 reserved
mb86830 series 67 (3)instruction cache tag (ictag) asi = 0x0c capacity 16 kb bank 1:address = 0x00000000 h to 0x00001fe0 h (+32) bank 2:address = 0x80000000 h to 0x80001fe0 h (+32) capacity 8 kb bank 1:address = 0x00000000 h to 0x00000fe0 h (+32) bank 2:address = 0x80000000 h to 0x80000fe0 h (+32) capacity 4 kb bank 1:address = 0x00000000 h to 0x000007e0 h (+32) bank 2:address = 0x80000000 h to 0x800007e0 h (+32) capacity 2 kb bank 1:address = 0x00000000 h to 0x000003f0 h (+16) bank 2:address = 0x80000000 h to 0x800003f0 h (+16) capacity 1 kb bank 2:address = 0x80000000 h to 0x800003f0 h (+16) bit 31 to bit 13 :address tag (rst = x) bit 12 :capacity 16 kb = , other =

bit 11 :capacity 16 kb, 8 kb = , other =

bit 10 :capacity 16 kb, 8 kb, 4 kb = _{(valid = 1, invalid = 0, rst = 0) capacity 2 kb, 1 kb = bit 9 to bit 6 :sub block valid (valid = 1, invalid = 0,rst = 0) bit 4 to bit 2 :capacity 16 kb, 8 kb, 4 kb = _{(valid = 1, invalid = 0, rst = 0) capacity2 kb, 1 kb = [dont care for read] bit 5 :user/supervisor (user = 0, supervisor = 1, rst = x) bit 1 :capacity1 kb = , other= lru (rst = 0) * bit 0 :entry lock (lock = 1, unlock = 0, rst = 0) *:bank only, bank 2 is reserved x:dont care (4)instruction cache invalidate register (icinvld)[wite only] asi = 0x0c capacity 16 kb bank 1:address = 0x00008000 h bank 2:address = 0x80008000 h other bank 1:address = 0x00001000 h bank 2:address = 0x80001000 h bit 31 to bit 2 :reserved [0write] bit 1 :cache lru, lock bit clear (clear = 1, not clear = 0) bit 0 :valid bit clear (clear = 1, not clear = 0) bit ? 31 13 12 11 10 9 6 5 4 2 1 0 address tag bit ? 31 210 reserved

mb86830 series 68 (5)instruction cache data ram (icdata) asi = 0x0d capacity 16 kb bank 1:address = 0x00000000 h to 0x00001ffc h (+4) bank 2:address = 0x80000000 h to 0x80001ffc h (+4) capacity 8 kb bank 1:address = 0x00000000 h to 0x00000ffc h (+4) bank 2:address = 0x80000000 h to 0x80000ffc h (+4) capacity 4 kb bank 1:address = 0x00000000 h to 0x000007fc h (+4) bank 2:address = 0x80000000 h to 0x800007fc h (+4) capacity 2 kb bank 1:address = 0x00000000 h to 0x000003fc h (+4) bank 2:address = 0x80000000 h to 0x800003fc h (+4) capacity 1 kb bank 2:address = 0x80000000 h to 0x800003fc h bit 31 to bit 0:data (rst = x) x:dont care (6)data cache tag (dctag) asi = 0x0e capacity 16 kb bank 1:address = 0x00000000 h to 0x00001fe0 h (+32) bank 2:address = 0x80000000 h to 0x80001fe0 h (+32) capacity 8 kb bank 1:address = 0x00000000 h to 0x00000fe0 h (+32) bank 2:address = 0x80000000 h to 0x80000fe0 h (+32) capacity 4 kb bank 1:address = 0x00000000 h to 0x000007e0 h (+32) bank 2:address = 0x80000000 h to 0x800007e0 h (+32) capacity 2 kb bank 1:address = 0x00000000 h to 0x000003f0 h (+16) bank 2:address = 0x80000000 h to 0x800003f0 h (+16) capacity 1 kb bank 2:address = 0x80000000 h to 0x800003f0 h (+16) bit 31 to bit 13 :address tag (rst = x) bit 12 :capacity 16 kb = , other = bit 11 :capacity 16 kb, 8 kb = , other = bit 10 :capacity 16 kb, 8 kb, 4 kb = _{(valid = 1, invalid = 0, rst = 0) capacity 2 kb, 1 kb = bit 9 to bit 6 :sub block valid (valid = 1, invalid = 0,rst = 0) bit 4 to bit 2 :capacity 16 kb, 8 kb, 4 kb = _{(valid = 1, invalid = 0, rst = 0) capacity 2 kb, 1 kb = [dont care for read] bit 5 :user/supervisor (user = 1, supervisor = 0, rst = x) bit 1 :capacity 1 kb = , other = lru (rst = 0) * bit 0 :entry lock (lock = 1, unlock = 0, rst = 0) *:bank 1 only, bank 2 is reserved x:dont care bit ? 31 0 data bit ? 31 13 12 11 10 9 6 5 4 2 1 0 address tag

mb86830 series 69 (7)data cache invalidate register (dcinvld)[wite only] asi = 0x0e capacity 16 kb bank 1:address = 0x00008000 h bank 2:address = 0x80008000 h other bank 1:address = 0x00001000 h bank 2:address = 0x80001000 h bit 31 to bit 2 :reserved [0write] bit 1 :cache lru, lock bit clear (clear = 1, not clear = 0) bit 0 :valid bit clear (clear = 1, not clear = 0) (8)data cache data ram(dcdata) asi = 0x0f capacity 16 kb bank 1:address = 0x00000000 h to 0x00001ffc h (+4) bank 2:address = 0x80000000 h to 0x80001ffc h (+4) capacity 8 kb bank 1:address = 0x00000000 h to 0x00000ffc h (+4) bank 2:address = 0x80000000 h to 0x80000ffc h (+4) capacity 4 kb bank 1:address = 0x00000000 h to 0x000007fc h (+4) bank 2:address = 0x80000000 h to 0x800007fc h (+4) capacity 2 kb bank 1:address = 0x00000000 h to 0x000003fc h (+4) bank 2:address = 0x80000000 h to 0x800003fc h (+4) capacity 1 kb bank 2:address = 0x80000000 h to 0x800003fc h (+4) bit 31 to bit 0 :data (rst = x) x:dont care bit ? 31 210 reserved bit ? 31 0 data

mb86830 series 70 16. interrupt controller (irc) (1)trigger mode 0 register (trgm0) cs3# = l, address<9:2> = 0x00 bit 31 to bit 16 :reserved [0write, dont care for read] bit 15 to bit 0 :trigger mode (high level = 00, low level = 01, high edge = 10, low edge = 11, rst = 00) (2)trigger mode 1 register (trgm1) cs3# = l, address<9:2> = 0x01 bit 31 to bit 16 :reserved [0write, dont care for read] bit 15 to bit 2 :trigger mode (high level = 00, low level = 01, high edge = 10, low edge = 11, rst = 00) bit 1 to bit 0 :reserved [0write, read0] (3)request sense register (reqsns)[read only] cs3# = l, address<9:2> = 0x02 bit 31 to bit 16 :reserved [dont care for read] bit 15 to bit 1 :request sense 15 to request sense 1 (rst = 0) bit 0 :reserved [read0] (4)request clear register (reqclr)[wite only] cs3# = l, address<9:2> = 0x03 bit 31 to bit 16 :reserved [0write] bit 15 to bit 1 :request clear 15 to request clear 1 (clear = 1, not clear = 0) bit 0 :reserved [0write] (5)interrupt mask register (imask) cs3# = l, address<9:2> = 0x04 bit 31 to bit 16 :reserved [0write, dont care for read] bit 15 to bit 1 :mask 15 to mask 1 (mask = 1, not mask = 0, rst = 1) bit 0 :irl mask (mask = 1, not mask = 0, rst = 0) bit ? 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 bit ? 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 0 0 bit ? 31 16 15 1 0 reserved request sense 15 to request sense 1 0 bit ? 31 16 15 1 0 reserved request clear 15 to request clear 1 0 bit ? 31 16 15 1 0 reserved mask 15 to mask 1 im

mb86830 series 71 (6)irl latch/clear register (irlat) cs3# = l, address<9:2> = 0x05 bit 31 to bit 16 :reserved [0write, dont care for read] bit 15 to bit 5 :reserved [0write, read"0"] bit 4 :irl clear [wite only] (clear = 1, not clear = 0) bit 3 to bit 0 :irl latch [read only] (rst = 0000) (7)irc mode register (imode) cs3# = l, address<9:2> = 0x06 bit 31 to bit 16 :reserved [0write, dont care for read] bit 15 to bit 2 :reserved [0write, read0] bit 1 to bit 0 :irc mode [ircmd] (disable = 00, enable = 01, rst = 00) 17. dram controller (1)dram bank configuration register (dbankr) cs3# = l, address<9:2> = 0x08 bit 31 :access error [err] (error = 1, no error = 0, rst = x, 0write clear) bit 30 to bit 11 :reserved [0write, dont care for read] bit 10 to bit 9 :dram start address [stadr] (rst = 01) bit 8 :hyper page enable [he] (page mode dram = 0, edo dram = 1, rst = 0) bit 7 :dram type[tp] (4cas-1we= 0, 4we -1cas = 1, rst = 0) bit 6 to bit 4 :column address [col] (rst = 011) bit 3 to bit 0 :bank size [bksize] (rst = 0011) x:dont care (2)dram timing register (dtimr) cs3# = l, address<9:2> = 0x09 bit 31 to bit 5 :reserved [0write, dont care for read] bit 4 :ras#precharge time specification bits [t rps ] at self-refresh (2 cycle = 0, 4 cycle = 1, rst = 1) bit 3 to bit 2 :ras#pulse width specification bit [t rascbr ] at cbr refresh (1 cycle = 00, 2 cycle = 01, 3 cycle = 10, rst = 01) bit 1 :cas#pulse width specification bit [t cas ] (1 cycle = 0, 2 cycle = 1, rst = 1) bit 0 :ras#precharge width specification bit [t rp ] (1 cycle = 0, 2 cycle = 1, rst = 0) bit ? 31 16 15 5 4 3 0 reserved reserved cl irl bit ? 31 16 15 2 1 0 reserved reserved ircmd bit ? 31 11 10 9 8 7 6 4 3 0 err reserved stadr he tp col bksize bit ? 31 54 3 2 1 0 reserved t rps t rascbr t cas t rp

mb86830 series 72 18. dsu (debugging support unit )(mb86832/834) (1)instruction address descriptor register (instadr) asi = 0x01, address = 0x0000ff00 h to 0x0000ff04 h bit 31 to bit 2 :instruction address compare data (rst = 0x00000000 h ) bit 1 to bit 0 :reserved [0write, dont care for read] (2)data address descriptor register (dataadr) asi = 0x01, address = 0x0000ff08 h to 0x0000ff0c h bit 31 to bit 0 :data address compare data (rst = 0x00000000 h ) (3)data value descriptor register (dvdr) asi = 0x01, address = 0x0000ff10 h bit 31 to bit 0 :data value (rst = 0x00000000 h ) (4)data value descriptor register/mask register (dvdmsk) asi = 0x01, address = 0x0000ff14 h bit 31 to bit 0 :data/mask value (rst = 0x00000000 h ) (5)debug control register (dsucr) asi = 0x01, address = 0x0000ff18 h bit 31 to bit 24 :asi value2 (rst = 0x00) bit 23 to bit 16 :asi value1 (rst = 0x00) bit 15 :instruction user/supervrisor2 (supervrisor = 1, user = 0, rst = 0) bit 14 :instruction user/supervrisor1 (supervrisor = 1, user = 0, rst = 0) bit 13 to bit 9 :reserved bit 8 :enable data address2 break (enable = 1, disable = 0, rst = 0) bit 7 :enable data address1 break (enable = 1, disable = 0, rst = 0) bit 6 :enable instruction address2 break (enable = 1, disable = 0, rst = 0) bit 5 :enable instruction address1 break (enable = 1, disable = 0, rst = 0) bit 4 :single step (on = 1, off = 0, rst = 0) bit 3 to bit 2 :data value transaction type (rst = 0x0) bit ? 31 21 0 instruction address compare data reserved bit ? 31 0 data address compare data bit ? 31 0 data value bit ? 31 0 data/mask value bit ? 31 24 23 16 15 14 1 3 9 876543210 asi value2 asi value1 reserved

mb86830 series 73 bit 1 :data value condition (outside = 1, inside = 0, rst = 0) bit 0 :data value mask (mask = 1, range = 0, rst = 0) (6)debug status register (dsr) asi = 0x01, address = 0x0000ff1c h bit 31 to bit 6 :reserved [0write, dont care for read] bit 5 :data address 2 match (match = 1, not match = 0, rst = 0) bit 4 :data address 1 match (match = 1, not match = 0, rst = 0) bit 3 :instruction address 2 match (match = 1, not match = 0, rst = 0) bit 2 :instruction address 1 match (match = 1, not match = 0, rst = 0) bit 1 :emuenbl [read only] bit 0 :emubrk [read only] 19. clock gear (not supported in mb86831-66,80) internal clock control/status register (iccs) cs3# = l, address<9:2> = 0x0b bit 31 to bit 7 :reserved [0write, dont care for read] bit 6 to bit 4 :internal clock status [clkst] bit 3 :internal clock change enable [ce] (enable = 1, disable = 0, rst = 0) bit 2 to bit 0 :internal clock select [clksel] bit 3 bit 2 type 0 0 break only on loads 0 1 break only on stores 1 0 break on load or store 1 1 break always bit ? 31 6543210 reserved bit ? 31 76 4 3 2 0 reserved clkst ce clksel clkst internal clock 100 1 101 2 110 3 111 4 011 5 010 reserved 001 000

mb86830 series 74 ? register explanation internal clock control/status register (iccs) bit 31 to bit 7 :reserved [0write, dont care for read] bit 6 to bit 4 :clkst (internal clock status)(an initial value is a set point of external terminal clksel2, clksel1, and clksel0. ) can know the multiplication rate that cpu works by the bit which shows internal clock. bit 3 :ce (internal clock change enable)(initial value 0) internal clock change inable bit.internal clock is changed according to the clksel bit according to this value at sleep mode (low power consumption mode). 1: internal clock is changed by the clksel bit. 0: no change internal clock. it is necessary to set 1 in this bit to change internal clock before sleep mode (low power con- sumption mode) is set. bit 2 to bit 0 :clksel (internal clock select) internal clock specification bit. 20. general-purpose 16-bit timer (mb86836) bit ? 31 76 432 0 reserved clkst ce clksel clkst internal clock 100 1 101 2 110 3 111 4 011 5 010 reserved 001 000 (1) prescaler0 (prs0) cs3# = l, address<9:2> = 0x0c bit ? 31 16 15 14 13 11 10 8 7 0 reserved ex test reserved select prescale value bit 31 to bit 16 bit 15 bit 14 bit 13 to bit 11 bit 10 to bit 8 bit 7 to bit 0 :reserved [0write, dont care for read] :external clock [0write] support to only internal clock mode :test [0write] :reserved [0write, dont care for read] :select (rst = 000) :prescale value (rst = 01)

mb86830 series 75 for details on each register, refer to the manual for the mb86942. 21. notes on register setting (1)cache/biu control register ? to set cache enable or cache disable, be sure to insert at least three nop instructions after the enable or disable instruction. ? the non-cacheable bit (bit 9, bit 8) and cacheability enable bit (bit 7) cannot be read. (2) timer control register (tcr) cs3# = l, address<9:2> = 0x0d bit ? 31 16 15 14 13 12 11 10 9 8 7 6 5 3 2 0 reserved bit 31 to bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 to bit 9 bit 8 to bit 7 bit 6 bit 5 to bit 3 bit 2 to bit 0 :reserved [0write, dont care for read] :value of out signal :value of in signal :reserved [0write, dont care for read] :test [0write] :count enable (enable = 1, disable = 0, rst = 0) :clock select (internal clock = 0, prescaler clock = 2, dont use = 1 or 3, rst = 0) :out signal control (keep = 0, set = 1, reset = 2, dont use = 3) :invert (true = 0, invert = 1, rst = 0) :mode select :event select (3) reload value register (rvr) cs3# = l, address<9:2> = 0x0e bit ? 31 16 15 0 reserved reload value bit 31 to bit 16 bit 15 to bit 0 :reserved [0write, dont care for read] :reload value (4) count value register (cvr) [read only] cs3# = l, address<9:2> = 0x0f bit ? 31 16 15 0 reserved count value bit 31 to bit 16 bit 15 to bit 0 :reserved [0write, dont care for read] :count value

mb86830 series 76 (2)bus control register ? enable burst transfer after setting cache enable. to set cache disable, disable burst transfer in advance. (3)system support control register ? set cache enable before setting dram burst enable. to set cache disable, disable the dram burst enable bit. ? before setting dram burst enable, be sure to set burst enable using the bus control register. ? the samepage# pin may become l at the first cs4 access after setting same page enable. ? the same page circuit holds previous data even after the bus master is changed. ? set the same page mask register before setting same page enable to 1. ? before changing the same page enable (bit 5) setting, set cache disable. ? set all of the address range specifier registers and address mask registers before setting cs enable to 1. (set all of the address range specifier registers and address mask registers even if any cs is not to be used.) ? before changing the cs enable (bit 4) setting, set cache disable. ? when setting the programmable wait-state, be sure to set the wait state specifier register. (4)wait state specifier register ? do not set the wait enable bit and the single cycle non burst mode bit to 1 at the same time. ? if the single cycle non burst mode bit is set to 1 in the burst mode, the ready signal is generated in one cycle regardless of the setting of the single cycle burst mode bit. ? when setting the cs3 wait state specifier register, be sure to set the override bit to1. (the wait state bit can also be set to 1.) when the half-word load instruction is executed with cs3 in 16-bit bus mode, the cpu accesses twice but the ready signal from the peripheral resource is generated only once. therefore the cpu hangs at the second access. to generate the second ready signal, set the wait enable bit to 1 (the cpu discards the data received at the second access). (5)bus width/cacheable register ? in the dram controller enable state with cs4# = l, cs5 is handled as a non-cacheable signal. ? in the dram controller enable state, the cs5 bus width follows the cs4 bus width setting. when the cs4 bus width control bit has been set to (10) 2 , for example, the cs5 bus width is forced to be set to (10) 2 . ? the cs3 bus width can be set only to the 16-bit or 32-bit bus width. when the 16-bit bus width is set, use half-word load (address 0) or half-word store (address 0) to access the interrupt controller (irc) and dram controller registers. (6)dram refresh timer register ? be sure to set the test mode bit to 0. otherwise, tovf# may not become l. ? since the timer performs counting based on the external clock, it is not affected by the multiplier circuit. (7)sleep mode register ? to set the sleep mode (low power consumption mode), disable the caches. ? the instruction to set the sleep mode (low power consumption mode) must be followed by at least three nop instructions. (8)trigger mode register ? set the interrupt mask register to (ffff) 16 before changing the trigger mode.

mb86830 series 77 ? the request sense register may contain 1 when the trigger mode is changed. therefore, issue request clear before canceling interrupt masks. the interrupt controller (irc) and dram controller registers cannot be accessed until cs3# becomesl. (9)cache invalidate register when the caches are off, write to the cache invalidate register. (10)internal clock control/status register to change clock multiplication by setting the ce bit in the internal clock control/status register to 1, input the l pulse to the wkup# pin at least 4000 clkin after entering the sleep mode.

mb86830 series 78 n orderinginformation part number package remarks mb86831pfv plastic qfp 176-pin (fpt-176p-m01) mb86831-80pfv plastic qfp 176-pin (fpt-176p-m01) mb86832-66pfv plastic qfp 176-pin (fpt-176p-m01) mb86832- 80pfv plastic qfp 176-pin (fpt-176p-m01) mb86832-100pfv plastic qfp 176-pin (fpt-176p-m01) mb86833pmt2 plastic lqfp 144-pin (fpt-144p-m08) mb86834pfv plastic qfp 176-pin (fpt-176p-m01) mb86834-120pfv plastic qfp 176-pin (fpt-176p-m01) MB86835pmt2 plastic lqfp 144-pin (fpt-144p-m08) mb86836pmt2 plastic lqfp 144-pin (fpt-144p-m08) mb86836-108pmt2 plastic lqfp 144-pin (fpt-144p-m08) under development mb86836pbt plastic fbga 144-pin (bga-144p-m02) mb86836-108pbt plastic fbga 144-pin (bga-144p-m02) under development

mb86830 series 79 n package dimensions (continued) 176-pin plastic qfp (fpt-176p-m01) dimensions inmm (inches) c 1995 fujitsu limited f176001s-3c-3 details of "a" part details of "b" part 0.50?.20(.020?008) 0 10 0.40(.016)max 0.15(.006)max 0.25(.010) 0.20(.008) 0.10(.004) "a" "b" 26.60?.20(1.047?008)sq 24.00?.10(.945?004)sq 0.15?.05 (.006?002) 25.60 21.50 0(0)min (stand off) index 0.20?.10 (.008?004) 0.08(.003) m 1 44 45 88 89 132 133 176 (.846) ref (1.008) nom lead no. 0.50(.0197)typ 3.85(.152)max (mounting height)

mb86830 series 80 (continued)i (continued) 144-pin plastic lqfp (fpt-144p-m08) dimensions inmm (inches) c 1995 fujitsu limited f144019s-1c-2 details of "a" part details of "b" part 0.50?.20(.020?008) 0 10 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 22.00?.30(.866?012)sq 20.00?.10(.787?004)sq 0.20?.10 (.008?004) 0.08(.003) m 0.15?.05 (.006?002) 1.70(.67)max 0(0)min (stand off) 21.00 17.50 (.827) nom (.686) ref 0.10(.004) "a" "b" 36 37 72 73 108 109 144 1 index 0.50(.0197)typ lead no. (mounting height)

mb86830 series 81 (continued) 144-pin plastic fbga (bga-144p-m02) dimensions inmm (inches) c 1998 fujitsu limited b144002s-2c-2 12.00?.10(.472?004)sq .049 ?004 +.008 ?.10 +0.20 1.25 (mounting height) 0.38?.10(.015?004) (stand off) 0.10(.004) c0.80(.031) index 9.60(.378)ref 0.80(.031)typ 1 2 3 4 5 6 7 8 9 10 11 lkjhgfedcba 144-0.45?.10 (144-.018?004) m 0.08(.003) 12 13 m n

mb86830 series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9909 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.}}}}

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